83 Commits

Author	SHA1	Message	Date
Thomas Harte	bc5727af14	Switch to = default.	2024-02-16 21:50:15 -05:00
Thomas Harte	b61317ba7e	Continue conversion of logging.	2024-01-19 22:02:26 -05:00
Thomas Harte	a3d37640aa	Switch include guards to #pragma once.	2024-01-16 23:34:46 -05:00
Thomas Harte	a5038259bc	Add admission.	2023-08-21 19:30:34 -04:00
Thomas Harte	bb84a5a474	Enable various ADB-controller interrupts.	2023-08-21 15:35:13 -04:00
Thomas Harte	8578dfbf22	Eliminate various other errant spaces.	2023-05-16 16:40:09 -04:00
Thomas Harte	28c79b2885	Eliminate redundant [space][tab] pairs.	2023-05-12 14:14:45 -04:00
Thomas Harte	2b56b7be0d	Simplify namespace syntax.	2023-05-10 16:02:18 -05:00
Thomas Harte	cbf5a79ee8	Takes a swing at improper key repeat.	2021-02-28 16:46:09 -05:00
Thomas Harte	5d1970d201	Adds a hacky different guess at how register access might work.	2021-02-19 21:46:18 -05:00
Thomas Harte	2e9065b34c	Increases number of fixed initial values.	2021-02-18 22:48:53 -05:00
Thomas Harte	2a45e7a8d4	Slows timer X, to what may or may not be correct.	2021-02-15 16:40:27 -05:00
Thomas Harte	f8f0ff0fae	Add timer X counting. ... Still no interrupts.	2021-02-15 16:29:25 -05:00
Thomas Harte	f5dcff2f29	Honours interrupt vector.	2021-02-15 15:05:56 -05:00
Thomas Harte	eccf5ca043	Makes first effort to wire up the ADB vertical blank input. ... However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.	2021-02-14 22:20:58 -05:00
Thomas Harte	c284b34003	Resolves inability of ADB microcontroller to read its own ROM (!)	2021-02-13 17:53:40 -05:00
Thomas Harte	2c4dcf8843	Edges towards implementing an ADB device.	2021-02-12 21:50:24 -05:00
Thomas Harte	e83b2120ce	Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.	2021-02-10 21:46:56 -05:00
Thomas Harte	3c7f9a43ad	Merge branch 'AppleIIgs' of github.com:TomHarte/CLK into AppleIIgs	2021-02-08 18:43:27 -05:00
Thomas Harte	82312d3b59	Provide a more convincing version of port output.	2021-02-08 18:14:08 -05:00
Thomas Harte	93a80a30d3	With correct divider appears to get reset requests posted.	2021-02-07 23:05:01 -05:00
Thomas Harte	77b1efd176	Sets sensible 'reset' values.	2021-02-07 21:53:57 -05:00
Thomas Harte	acfab1dfb3	Starts to make some effort at timers.	2021-02-06 21:02:44 -05:00
Thomas Harte	819e9039ab	Corrects printed target address for ZeroPageRelative.	2021-02-04 20:54:31 -05:00
Thomas Harte	b8c6d4b153	Rips out my high-level ADB microcontroller protocol implementation. ... Adds just enough that the main computer validates the ADB controller as present and talking.	2021-01-30 17:53:27 -05:00
Thomas Harte	5eddc92846	Implements direction registers.	2021-01-28 21:06:11 -05:00
Thomas Harte	dcc2fe0990	Improves M50470 entry-point detection, adds test output.	2021-01-26 21:29:17 -05:00
Thomas Harte	cc90935abd	Starts to provide just a touch of reflection.	2021-01-26 19:22:00 -05:00
Thomas Harte	413e42e1b6	Attempts to fix BBC. ... But thereby stops all ADB output.	2021-01-25 22:34:03 -05:00
Thomas Harte	fc4bda0047	Experimentally flipping interpretation of the output bit gives something closer to coherent.	2021-01-25 22:02:39 -05:00
Thomas Harte	c8beb59172	Attempts properly to track ADB bus activity. ... Output is not yet a valid ADB stream. Work to do.	2021-01-25 17:43:22 -05:00
Thomas Harte	8789ffda15	Corrects performer storage, RMW/W confusion, implicit casts, port readback.	2021-01-24 22:30:42 -05:00
Thomas Harte	e8e604dc3c	Attempts to wire up M50470 and GLU. ... Resulting in an unexpected interest in R15. Bugs to find, I guess.	2021-01-24 18:07:05 -05:00
Thomas Harte	57e0fdfadc	Ensures ADB microcontroller is clocked. ... And runs at the 'correct' speed (i.e. modulo my instruction-by-instruction implementation).	2021-01-23 22:55:12 -05:00
Thomas Harte	36aebe0ff9	Posts cycle lengths.	2021-01-23 21:58:52 -05:00
Thomas Harte	051d2b83f4	Corrects TSX lookup.	2021-01-23 15:45:21 -05:00
Thomas Harte	17b12120eb	Corrects bit-selection shifts.	2021-01-21 23:13:00 -05:00
Thomas Harte	6e9ce50569	Corrects duration-based iteration.	2021-01-21 23:05:43 -05:00
Thomas Harte	adef2e9b4e	Starts formalising end conditions.	2021-01-21 22:36:44 -05:00
Thomas Harte	0fafbf5092	Completes M50740 instruction set.	2021-01-21 19:08:38 -05:00
Thomas Harte	c10c161d39	Implements ADC and SBC.	2021-01-21 18:53:24 -05:00
Thomas Harte	04024ca159	Adds BIT.	2021-01-20 21:41:43 -05:00
Thomas Harte	64d556f60f	Implements shifts and rotates.	2021-01-20 21:39:13 -05:00
Thomas Harte	8564e7406b	Corrects index-mode CMP, LDA.	2021-01-20 21:32:46 -05:00
Thomas Harte	ebdb58d790	Seemingly advances to the first indefinite loop.	2021-01-20 21:18:52 -05:00
Thomas Harte	cf8afc70b2	Takes a swing at BBC, BBS.	2021-01-20 20:52:04 -05:00
Thomas Harte	4f02e8fbaf	Knocks off the low-hanging instruction fruit.	2021-01-20 20:41:35 -05:00
Thomas Harte	6e618a6bb7	Adds a list of missing instructions. ... Not looking too bad; subject to not yet having a strategy for interrupts, timing, nothing yet implemented for timers, IO ports...	2021-01-20 20:37:35 -05:00
Thomas Harte	df1bc18fb3	Pushes ahead to what will be my first interaction with the T flag.	2021-01-20 20:27:09 -05:00
Thomas Harte	9f12ce2fb8	Corrects RTS, adds the remainder of the direct flag manipulations.	2021-01-20 20:16:55 -05:00