6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-09 01:10:10 +00:00
Code Issues Projects Releases Wiki Activity
9,521 Commits 8 Branches 121 Tags 496 MiB
b67790df7d
Commit Graph

1172 Commits

Author SHA1 Message Date
Thomas Harte
cce449ba8f Merge branch 'master' into EventDriven 2022-07-12 15:06:52 -04:00
Thomas Harte
4ddbf095f3 Fully banish flush from the processors. 2022-07-12 10:49:53 -04:00
Thomas Harte
3a2d27a636 Correct for switched BRK presumption. 2022-07-08 11:15:48 -04:00
Thomas Harte
a5b7ef5498 Further compact list of potential switch targets. 2022-06-30 08:31:51 -04:00
Thomas Harte
11305c2e6b Eliminate large gap in case values. 2022-06-29 21:40:48 -04:00
Thomas Harte
b1d8a45339 Just disable the diagnostic. 2022-06-29 21:13:00 -04:00
Thomas Harte
c133f80c73 Try a compiler-specific attribute. 2022-06-29 19:20:44 -04:00
Thomas Harte
58b04cdfa4 Switch to an alternative form of avoiding unused goto warnings. 2022-06-29 19:08:41 -04:00
Thomas Harte
c2938a4f63 Avoid potential classic macro error with address. 2022-06-29 15:09:52 -04:00
Thomas Harte
e0ec3c986d Ensure appropriate data bus size. 2022-06-25 21:07:29 -04:00
Thomas Harte
fc1952bf42 Add an automatic bus size selector. 
This fixes the Jeek test.
 2022-06-25 16:28:06 -04:00
Thomas Harte
4467eb1c41 Ensure relevant throwaway stack reads use the previous stack address. 
TODO: can CycleFetchPreviousThrowaway be used more widely?
 2022-06-24 14:00:03 -04:00
Thomas Harte
1c1ce625a7 Vector reads signal VDA. 2022-06-24 10:37:39 -04:00
Thomas Harte
069a057a94 Resolve assumption of arithmetic shifts. 2022-06-24 07:26:07 -04:00
Thomas Harte
4ed3b21bf3 Decimal SBC tweak: negative partial results don't cause carry. 2022-06-23 21:58:09 -04:00
Thomas Harte
a23b0f5122 Map STA (d), y to correct calculator. 2022-06-23 20:57:47 -04:00
Thomas Harte
da552abf75 Fix BIT overflow flag. 2022-06-23 15:24:51 -04:00
Thomas Harte
380b5141fb Be overt about conversion wanted here. 2022-06-23 13:03:26 -04:00
Thomas Harte
66775b2c4e Always consume a second cycle in 16-bit mode. 2022-06-23 12:46:51 -04:00
Thomas Harte
2c12a7d968 Make absolutely sure there's no address bit 24. 2022-06-23 12:12:02 -04:00
Thomas Harte
5a97c09238 Flip internal presumption on the BRK flag. 2022-06-23 11:23:00 -04:00
Thomas Harte
3112376943 Don't include DBR in direct indexed indirect. 2022-06-23 11:03:37 -04:00
Thomas Harte
ecfd17a259 Report a 1 in the stack pointer high byte when in emulation mode. 
It has one internally, it just wasn't previously exposed via this method.
 2022-06-22 15:55:34 -04:00
Thomas Harte
a72dd96dc6 Page boundary crossing is free outside of emulation mode. 2022-06-22 15:31:30 -04:00
Thomas Harte
944e5ebbfa Take another run at IO addresses. 2022-06-22 15:28:11 -04:00
Thomas Harte
76767110b7 Fix overflow for 8-bit calculations; essentially a revert for ADC. 2022-06-22 15:18:47 -04:00
Thomas Harte
7dcfa9eb65 65816: improve decimal calculations, posted IO addresses, read/write during redundant read-modify-write cycle. 2022-06-21 14:33:06 -04:00
Thomas Harte
ec98736bd7 Ensure IO cycles don't produce an address of (PC+1). 2022-06-21 11:41:05 -04:00
Thomas Harte
586ef4810b Add restart_operation_fetch, to aid with testing. 2022-06-18 16:25:57 -04:00
Thomas Harte
a0bc332fe6 Taking a second parse, prefer non-lookup-table solutions. 2022-06-17 11:55:38 -04:00
Thomas Harte
b0ab5b7b62 Simplify Microcycle helpers. 2022-06-16 21:34:24 -04:00
Thomas Harte
dc8103ea82 Fix return address following a STOP. 2022-06-16 15:10:35 -04:00
Thomas Harte
7d00b50e13 Fix upper/lower_data_select; simplify value8_low. 2022-06-15 21:11:31 -04:00
Thomas Harte
12b058867e Correct very minor typo. 2022-06-15 19:34:54 -04:00
Thomas Harte
8ff09a1923 Fix value8_high. 2022-06-15 19:34:49 -04:00
Thomas Harte
62fa0991ed Disallow copying, add some basic asserts. 2022-06-15 19:34:43 -04:00
Thomas Harte
24823233ff Add spurious interrupt support. 2022-06-15 11:00:27 -04:00
Thomas Harte
bd056973ba Don't allow STOP state to block execution. 2022-06-15 10:56:45 -04:00
Thomas Harte
5420fd5aa3 Fix: new status word is still in prefetch. 2022-06-15 10:54:34 -04:00
Thomas Harte
93615f6647 Apply new status before entering STOP loop. 2022-06-15 10:50:03 -04:00
Thomas Harte
0ace9634ce Fix MOVEA. 2022-06-14 21:56:48 -04:00
Thomas Harte
48d51759cd At huge copy-and-paste cost, fix MOVE.l. 2022-06-14 21:22:28 -04:00
Thomas Harte
bfd0b683bf Extend MOVE.b fix to cover MOVE.w. 2022-06-14 17:04:11 -04:00
Thomas Harte
61e0f60e94 Add specialised MOVE.b to correct bus sequencing. 
This is a bit of a trial balloon; .w and .l to come.
 2022-06-13 21:49:00 -04:00
Thomas Harte
7fa715e37a Provide more thorough documentation. 2022-06-13 15:27:23 -04:00
Thomas Harte
e066546c13 Resolve PEA timing errors. 2022-06-13 14:08:42 -04:00
Thomas Harte
4a75691005 Avoid double conditional for CalcEffectiveAddressIdleFor8bitDisplacementAndPreDec. 2022-06-13 10:27:22 -04:00
Thomas Harte
8ada73b283 Use the outer switch for addressing mode dispatch, saving a lot of syntax. 2022-06-13 08:57:49 -04:00
Thomas Harte
2a9a05785c Bus and address error don't affect interrupt level. 2022-06-11 21:10:24 -04:00
Thomas Harte
c3345dd839 Fix MOVEM timing. 2022-06-10 21:52:07 -04:00