Thomas Harte
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b6f51474ff
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Ensured that -description can handle the newly-captured bus actions.
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2017-06-17 18:20:30 -04:00 |
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Thomas Harte
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0f18768091
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Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.
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2017-06-17 18:19:25 -04:00 |
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Thomas Harte
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50cd617bd9
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Ensured test raises only the intentional failure exceptions.
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2017-06-15 22:33:46 -04:00 |
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Thomas Harte
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838b818cd3
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Finished transcribing first page of machine cycle documentation; several failures contained.
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2017-06-15 22:19:49 -04:00 |
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Thomas Harte
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cf795562bf
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Continued filling in tests, fleshing out what the test machine captures as a result.
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2017-06-15 20:59:59 -04:00 |
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Thomas Harte
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ac37424878
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Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.
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2017-06-15 19:06:59 -04:00 |
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Thomas Harte
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aed2827e7b
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Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
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2017-06-12 22:22:00 -04:00 |
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Thomas Harte
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50be3a24fe
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Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be.
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2017-06-11 13:30:08 -04:00 |
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Thomas Harte
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2190f60a89
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Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool.
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2017-06-04 15:46:35 -04:00 |
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Thomas Harte
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0eebfdb4cc
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Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.
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2017-06-04 15:39:37 -04:00 |
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Thomas Harte
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7811374b0f
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Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).
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2017-06-04 15:07:07 -04:00 |
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Thomas Harte
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87095b0578
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Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures.
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2017-06-04 14:04:26 -04:00 |
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Thomas Harte
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b642d9f712
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Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
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2017-06-03 21:54:42 -04:00 |
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Thomas Harte
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fd6623b5a5
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Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
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2017-06-03 21:22:16 -04:00 |
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Thomas Harte
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b3da16911f
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Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.
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2017-06-03 18:42:54 -04:00 |
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Thomas Harte
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e52892f75b
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Added a test of interrupt mode 1.
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2017-06-03 18:16:13 -04:00 |
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Thomas Harte
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8c41a0f0ed
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Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.
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2017-06-03 17:53:44 -04:00 |
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Thomas Harte
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3e9212aaff
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Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
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2017-06-03 17:41:45 -04:00 |
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Thomas Harte
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d14902700a
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Minor syntax and wiring fixes.
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2017-06-01 22:33:05 -04:00 |
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Thomas Harte
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c95c32a9fe
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Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.
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2017-06-01 22:31:04 -04:00 |
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Thomas Harte
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494ce073b5
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Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.
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2017-05-31 19:58:57 -04:00 |
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Thomas Harte
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5ff73faf48
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Ensured Zexall can pass.
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2017-05-31 19:55:06 -04:00 |
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Thomas Harte
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2f7f11e2e5
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Added diagnosis props.
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2017-05-31 06:54:25 -04:00 |
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Thomas Harte
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5119997122
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Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
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2017-05-30 22:41:23 -04:00 |
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Thomas Harte
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244b5ba3c2
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Added a proper termination condition for Zexall and, for now, a Mhz counter.
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2017-05-30 18:32:38 -04:00 |
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Thomas Harte
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960de7bd7b
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Marginally reduced test machine costs based on usage.
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2017-05-30 11:59:07 -04:00 |
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Thomas Harte
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4d4695032c
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Discovered that Zexall is just really slow. Disabled the address sanitiser, and started working towards a verifiable end.
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2017-05-29 21:46:00 -04:00 |
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Thomas Harte
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6d22f6fcd5
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Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being.
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2017-05-29 17:17:17 -04:00 |
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Thomas Harte
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8bfaa487ce
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Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).
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2017-05-29 17:13:24 -04:00 |
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Thomas Harte
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267b2add9a
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Adjusted for where FUSE nominally places timestamps. Down to 92 failures.
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2017-05-29 16:44:07 -04:00 |
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Thomas Harte
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d290e3d99e
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Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)
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2017-05-29 16:35:00 -04:00 |
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Thomas Harte
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a6a4c5a936
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Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.
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2017-05-29 15:57:27 -04:00 |
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Thomas Harte
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ed7b07c8b1
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Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct.
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2017-05-29 11:54:27 -04:00 |
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Thomas Harte
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d83dd17738
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[DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed.
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2017-05-29 11:40:56 -04:00 |
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Thomas Harte
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9ade0dcae3
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One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison.
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2017-05-29 11:06:23 -04:00 |
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Thomas Harte
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a329d85697
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Instituted memory value checks, flushing out seven new failures.
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2017-05-29 11:01:45 -04:00 |
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Thomas Harte
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c322410783
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Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation.
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2017-05-29 10:52:54 -04:00 |
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Thomas Harte
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b67331e018
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Fixing the OUT repetition group reduces the code to one failing test.
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2017-05-29 10:48:53 -04:00 |
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Thomas Harte
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ad56a9215c
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Implemented IN[I/D]x. 18 failures remaining.
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2017-05-29 10:12:33 -04:00 |
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Thomas Harte
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c56a5344b9
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Implemented CP[I/D]x.
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2017-05-29 08:54:00 -04:00 |
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Thomas Harte
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409c82ce73
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Implemented RLD and RRD. 34 failures remaining.
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2017-05-28 16:46:27 -04:00 |
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Thomas Harte
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6e83b7d6df
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Attempted to add a proper exit condition for Zexall.
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2017-05-28 15:13:47 -04:00 |
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Thomas Harte
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5a4d448cc1
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Corrected logical flags; now down to 68 failures, all of them on the ED page.
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2017-05-28 15:09:58 -04:00 |
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Thomas Harte
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6b66c8f304
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Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84.
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2017-05-28 14:50:51 -04:00 |
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Thomas Harte
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035df316aa
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FUSE seems to have inconsistent ideas about where b3 and b5 come from in more-complicated BIT instructions. So I'm not testing them for now. Within that reality, reduced to 102 failures.
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2017-05-27 23:54:53 -04:00 |
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Thomas Harte
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c7cb47a1d8
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Readded and then disabled my temporary one-test-only patch. Failures are currently at 237.
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2017-05-27 21:10:25 -04:00 |
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Thomas Harte
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98423c6e41
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Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues.
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2017-05-27 16:19:15 -04:00 |
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Thomas Harte
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33c3fa21e3
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Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672.
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2017-05-27 15:54:24 -04:00 |
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Thomas Harte
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9bc2b48d9b
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Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures.
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2017-05-26 23:23:33 -04:00 |
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Thomas Harte
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e4e71a1e5f
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Switched back to descriptive failures, but put a cap on them.
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2017-05-25 21:08:24 -04:00 |
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