Thomas Harte
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b7f88e8f61
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Filter is now a ClockReciever, affecting all sound output devices.
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2017-07-24 21:29:13 -04:00 |
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Thomas Harte
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8a2bdb8d22
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Converted the TimedEventLoop and the things that sit atop it into ClockReceivers.
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2017-07-24 21:19:05 -04:00 |
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Thomas Harte
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b82bef95f3
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Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
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2017-07-24 20:10:05 -04:00 |
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Thomas Harte
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8a0b0cb3d7
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Extended both classes to allow copy assignment, copy construction and implicit zero-length construction.
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2017-07-23 22:13:41 -04:00 |
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Thomas Harte
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1ba3f262a2
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Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles.
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2017-07-22 21:46:50 -04:00 |
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Thomas Harte
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8755824c64
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Added some documentation.
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2017-07-22 17:25:53 -04:00 |
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Thomas Harte
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64865b3f41
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Signedness fixes.
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2017-07-21 21:23:34 -04:00 |
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Thomas Harte
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53f0e1896b
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Made delay_time_ unsigned for safe comparison.
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2017-07-21 21:21:23 -04:00 |
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Thomas Harte
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aaa60dab12
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Fixed signedness of index.
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2017-07-21 21:21:01 -04:00 |
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Thomas Harte
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12f7e1b804
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Enshrined a default colour burst amplitude. Which now everybody relies on. The 102 figure is derived from the burst apparently being 40 IRE.
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2017-07-07 23:35:14 -04:00 |
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Thomas Harte
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eb8a2de5d6
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Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.
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2017-05-15 07:38:59 -04:00 |
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Thomas Harte
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e270b726b3
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Tweaked blue, increased saturation.
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2017-05-13 22:01:02 -04:00 |
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Thomas Harte
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44ce7fa54c
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Corrected luminances across the board, and PAL colours.
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2017-05-13 21:50:09 -04:00 |
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Thomas Harte
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b0142cf050
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Made an updated stab at NTSC colours.
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2017-05-13 14:29:36 -04:00 |
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Thomas Harte
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a340331229
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Introduced 1-bit of saturation, returning black and white as black and white.
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2017-05-11 21:31:58 -04:00 |
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Thomas Harte
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15d17c12d5
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Switched the 6560 to two bytes per pixel, since one isn't sufficient for precision and because mixing up the implementation might help me to figure out what's amiss.
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2017-05-09 21:22:01 -04:00 |
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Thomas Harte
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5998123868
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Added some consts, for a minor safety improvement.
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2017-05-06 19:53:24 -04:00 |
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Thomas Harte
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e01f3f06c8
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Completed curly bracket movement.
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2017-03-26 14:34:47 -04:00 |
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Thomas Harte
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a4c5eebd1e
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The latest Atari Age-discovered numbers suggest this starts up in 1024T mode.
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2017-03-21 18:22:50 -04:00 |
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Thomas Harte
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c445eaec3e
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Switched startup values, following a comment on AtariAge. May or may not be correct, the thread was speculative.
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2017-03-19 17:38:26 -04:00 |
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Thomas Harte
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e0bca1e37b
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Reinstated the 16 and 32 kb Atari pagers, and ensured the 6532 always starts in a valid state.
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2017-03-18 17:34:34 -04:00 |
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Thomas Harte
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d3257c345a
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Tested against public ROMs and corrected. Also moved the deferred adjustment into a more canonical place.
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2017-03-04 17:00:28 -05:00 |
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Thomas Harte
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e09b76bf32
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Fixed 'same value, then immediate increment, then proper counting increments' behaviour and ensured it takes one cycle to commit a value. Adjusted tests to match.
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2017-03-04 15:57:54 -05:00 |
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Thomas Harte
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ced644b103
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It seems likely that an AY divides its clock by 8, not 16. I had conflated wave frequency and counter clock.
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2017-01-11 22:03:01 -05:00 |
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Thomas Harte
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eca3995481
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Added a CRC check for read address, ensured CRC, lost data and record not found are initially reset.
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2017-01-01 21:00:25 -05:00 |
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Thomas Harte
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044c920a5b
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Made it more explicit that there are no unhandled cases.
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2017-01-01 20:56:52 -05:00 |
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Thomas Harte
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0df9ce5a76
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Made an attempt at read address. So superficially that leaves only the force interrupts.
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2017-01-01 20:55:09 -05:00 |
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Thomas Harte
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f94f34f053
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Made an attempt at read track. Which means process_input_bit can't just swallow syncs any more; it now reports them as tokens of type ::Sync.
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2017-01-01 20:39:19 -05:00 |
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Thomas Harte
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c994fa39f6
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Ensured spin-up doesn't occur if there's no motor line.
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2016-12-31 16:18:30 -05:00 |
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Thomas Harte
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1ea4f0d79d
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Made an attempt to implement 'write track' and ensure that 'write sector' can't end without announcing that it has ended writing.
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2016-12-31 16:01:44 -05:00 |
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Thomas Harte
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8eb21c6702
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The "MFM...Byte"s aren't MFM-specific, they're relevant to both FM and MFM encoding. So renamed them. Also slimmed syntax within MFM.cpp mostly where emigration from the Acorn disk analyser had left a residue of lengthy namespace specification.
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2016-12-31 15:25:11 -05:00 |
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Thomas Harte
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a8bc9d830e
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Removed leftover very temporary debugging aid.
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2016-12-28 23:03:05 -05:00 |
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Thomas Harte
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e4000bd060
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Added some even more verbose logging; slightly simplified write loop logic, and decided it's definitely write_byte that's responsible for CRC generator feeding.
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2016-12-28 21:24:19 -05:00 |
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Thomas Harte
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4adcb46665
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Fixed FM-mode CRC generation.
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2016-12-28 19:51:27 -05:00 |
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Thomas Harte
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1277a67f9a
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Introduced data_mode_ to replace is_reading_data_, representing that there are now three possible modes. When writing, any input from the read head won't affect the CRC generator.
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2016-12-28 19:26:21 -05:00 |
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Thomas Harte
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7a627b782d
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Reintroduced writing of MFM sync marks when writing a sector.
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2016-12-28 18:48:50 -05:00 |
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Thomas Harte
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a568172758
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Made steps towards proper CRC generation. Am currently comparing against Oric disk images, as — amongst other things — they include precomputed CRCs.
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2016-12-28 18:29:37 -05:00 |
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Thomas Harte
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9c0f622a2e
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Started working CRC checking into the 1770. Discovered immediately that my generated CRC does not match that built into the Oric disk images. So mine is pretty-much certainly wrong. An opportunity for learning!
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2016-12-26 16:46:26 -05:00 |
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Thomas Harte
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0490a47058
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Worked on the all-around framework for decoding sectors back from tracks when closing down a file. Hit the wall that the parser is more observant of CRCs than the WD. No, really. So I guess I have to stop avoiding that whole issue.
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2016-12-26 14:24:33 -05:00 |
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Thomas Harte
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83c433c142
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Deviated from the data sheet, which seems likely to be correct. Hence removed a whole load of the temporary logging.
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2016-12-26 12:48:49 -05:00 |
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Thomas Harte
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742c5df367
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With lots of logging arising temporarily, fixed bug whereby conversion to a patched track would lead to holding a track with a distinct measure of time, leading to improperly-placed patches.
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2016-12-25 22:00:39 -05:00 |
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Thomas Harte
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acc35885cd
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Attempted to reduce track invalidations.
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2016-12-25 20:38:25 -05:00 |
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Thomas Harte
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c0a1264ab0
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Slightly improved legibility.
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2016-12-25 20:19:47 -05:00 |
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Thomas Harte
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e2b829f68e
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Made an attempt to write the proper address mark.
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2016-12-25 20:15:07 -05:00 |
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Thomas Harte
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beaa868079
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Factored the MFM parser out into encodings.
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2016-12-25 20:00:57 -05:00 |
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Thomas Harte
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74e98fd097
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Made an attempt to write actual data (albeit that CRC calculation is still missing).
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2016-12-25 19:18:45 -05:00 |
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Thomas Harte
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98be6ede45
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Shuffled a little to reduce risk of overflow, ensured writing is a loop, still seem to be writing too quickly for some reason.
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2016-12-25 16:13:05 -05:00 |
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Thomas Harte
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d2ad2c756e
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Added enough shovelling to write rubbish for an entire sector.
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2016-12-25 15:46:49 -05:00 |
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Thomas Harte
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aceb7e3b6b
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Started implementing write sector on the 1770, immediately deciding it would be useful to have a callback for end-of-queued-data-written from disk controller. So had a go at implementing that, naively. More investigation required.
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2016-12-25 12:31:38 -05:00 |
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Thomas Harte
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901f19f89c
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Added enough stuff that SSDs attached to a 1770 will now reach the entry point for writing.
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2016-12-25 09:46:12 -05:00 |
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