156 Commits

Author	SHA1	Message	Date
Thomas Harte	bb910e14a4	Dealt with the CB page.	2017-06-18 18:01:33 -04:00
Thomas Harte	69ebbe019a	Completed ED page conversion. Rolling onwards...	2017-06-18 17:56:48 -04:00
Thomas Harte	0d39672d32	Fixing typos here and there, persuaded the first half of the ED table to compile.	2017-06-18 17:48:54 -04:00
Thomas Harte	0d1231980a	Advanced to getting specific warnings in the ed-page table. So that's progress.	2017-06-18 17:25:15 -04:00
Thomas Harte	82a015892b	Started adapting to the newly-segmented world.	2017-06-18 17:18:01 -04:00
Thomas Harte	194b7f60c5	Rephrased to allow non-conditional waits; expanded macros to cover all permitted lengths of read and write.	2017-06-18 17:08:50 -04:00
Thomas Harte	ebc7356db5	Reformulated the machine cycle slightly to support posting operation plus phase, thereby exposing the segue points at which waits might be inserted. So: to stick to the rule that CPUs expose the minimum amount of information sufficient completely to reconstruct bus activity. This breaks the Z80 for now.	2017-06-18 12:21:27 -04:00
Thomas Harte	e1a2580b2a	Renamed BusOperation to MachineCycle::Operation.	2017-06-17 21:53:45 -04:00
Thomas Harte	efc7f9df37	Combined I and R into a register pair.	2017-06-17 18:18:28 -04:00
Thomas Harte	aed2827e7b	Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.	2017-06-12 22:22:00 -04:00
Thomas Harte	b9dbb6bcf8	Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate.	2017-06-12 18:55:04 -04:00
Thomas Harte	d12e50eb02	Corrected "should I adjust history?" tests.	2017-06-11 16:41:34 -04:00
Thomas Harte	db30f53ab0	Added the capacity to back-date interrupt line changes within a machine cycle, so that machines which time themselves entirely within perform_machine_cycle can still be cycle accurate on those changes.	2017-06-11 13:31:02 -04:00
Thomas Harte	b55579c348	Fixed usage of flush: the subclass version is definitively used.	2017-06-06 17:52:44 -04:00
Thomas Harte	3df6eba237	Fixed: my HALT line wasn't actually halting. NOPs followed, but the PC just kept counting.	2017-06-05 10:35:03 -04:00
Thomas Harte	e940e02126	Added a short circuit to set_interrupt_line, mostly to make breakpoints slightly more convenient to place.	2017-06-05 09:37:19 -04:00
Thomas Harte	7f743c6fb0	Got explicit about permitted type conversions.	2017-06-04 18:40:59 -04:00
Thomas Harte	096551ab3e	Made a first attempt to hash out the ZX80's bus. Video output isn't yet going though. Can't seem to find clarity on whether horizontal sync is really programmatic. Let's see.	2017-06-04 18:32:23 -04:00
Thomas Harte	c485c460f7	Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.	2017-06-04 18:08:35 -04:00
Thomas Harte	d2637123c4	Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.	2017-06-04 17:55:19 -04:00
Thomas Harte	0eebfdb4cc	Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.	2017-06-04 15:39:37 -04:00
Thomas Harte	7811374b0f	Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).	2017-06-04 15:07:07 -04:00
Thomas Harte	a2f01b4a46	Corrected CPx bit 3 and 5 flags. I think only BIT n, (HL) with the famous MEMPTR reliance is preventing a complete pass by Zexall now.	2017-06-04 14:59:18 -04:00
Thomas Harte	f5c910beb7	Fixed LDIR/LDDR bit 3/5 flags. This seems once again to satisfy FUSE.	2017-06-04 14:18:04 -04:00
Thomas Harte	4e014ca748	Ensured BIT takes bits 5 and 3 from the computed address if used on indexed pages. That seems to cover 97 failures out of 100?	2017-06-04 14:13:38 -04:00
Thomas Harte	3ceef2005b	Pulled the Z80 from the MicroOpScheduler inheritance tree as it barely uses the thing, and that allows me to make the MicroOp structure private.	2017-06-03 19:17:34 -04:00
Thomas Harte	24c84ca6f5	Commented out as-yet-unimplemented features.	2017-06-03 19:10:23 -04:00
Thomas Harte	7898f643ac	Added bus request/acknowledge logic.	2017-06-03 19:09:47 -04:00
Thomas Harte	7bd45d308a	Error was simply failure of the interrupt-mode setter. Fixed.	2017-06-03 18:58:13 -04:00
Thomas Harte	b3da16911f	Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.	2017-06-03 18:42:54 -04:00
Thomas Harte	8c41a0f0ed	Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.	2017-06-03 17:53:44 -04:00
Thomas Harte	3e9212aaff	Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.	2017-06-03 17:41:45 -04:00
Thomas Harte	a2ec902773	Made an attempt at implementing all three modes of IRQ.	2017-06-03 17:07:05 -04:00
Thomas Harte	1c0130fd02	Cleaned up with a macro, and decided to make absolutely sure that DecodeOperation is functioning as intended by removing the MoveToNextProgram from fetch-decode-execute.	2017-06-03 12:19:25 -04:00
Thomas Harte	3e3d6f97f4	Edged towards being able to implement interrupt mode 0: created a special-case micro-op for incrementing the PC, and formalised that DecodeOperation is a terminal operation.	2017-06-03 12:16:21 -04:00
Thomas Harte	9c3bda0111	Attempted to round out NMI handling.	2017-06-03 11:30:12 -04:00
Thomas Harte	d14902700a	Minor syntax and wiring fixes.	2017-06-01 22:33:05 -04:00
Thomas Harte	c95c32a9fe	Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.	2017-06-01 22:31:04 -04:00
Thomas Harte	35e045d7a7	Made a first attempt at the correct segue into the three main kinds of interrupt, though the programs aren't written yet. So undefined behaviour would abound were an interrupt to occur. But it lets me figure out what effect the check has on performance. I hope little.	2017-06-01 22:16:22 -04:00
Thomas Harte	084e1f3d51	Added a latching of interrupt status before each bus operation, and reset and power-on inputs.	2017-06-01 21:40:08 -04:00
Thomas Harte	5b43cefb85	Started filling an appropriate mask variable with the interrupt request status right now. Which is step one towards implementing interrupts.	2017-06-01 20:34:52 -04:00
Thomas Harte	7d9b197383	Pulled the .get() call for fetch-decode-execute out of the main loop.	2017-06-01 18:28:04 -04:00
Thomas Harte	c9dd267ec1	Sketched an interface for signalling interrupts and pulled out some of the repetition in flag setting from ADD/ADC/SUB/SBC/CP.	2017-05-31 22:51:32 -04:00
Thomas Harte	a5254989f8	Rewired the Z80 not to use the program queue, as it's not proven a useful abstraction in practice and doing so yields an immediate 22% speed increase.	2017-05-31 20:15:56 -04:00
Thomas Harte	494ce073b5	Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.	2017-05-31 19:58:57 -04:00
Thomas Harte	b99e4210ba	Eliminated pointless abstraction; I ended up going indirect on instruction pages rather than scheduling methods.	2017-05-31 19:57:03 -04:00
Thomas Harte	d3b74cbc91	Set proper initial value for number_of_cycles_.	2017-05-31 19:55:51 -04:00
Thomas Harte	2f7f11e2e5	Added diagnosis props.	2017-05-31 06:54:25 -04:00
Thomas Harte	5119997122	Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.	2017-05-30 22:41:23 -04:00
Thomas Harte	b5c1773d59	Eliminated another conditional. Albeit a very predictable one.	2017-05-30 22:15:43 -04:00