1108 Commits

Author	SHA1	Message	Date
Thomas Harte	da61909ec5	Explain the purpose here.	2023-01-01 21:20:30 -05:00
Thomas Harte	5729ece7bb	Incompletely transitions towards more flexible clock ratios.	2023-01-01 14:20:45 -05:00
Thomas Harte	151f60958e	Relocate the 9918 implementation file.	2023-01-01 14:01:19 -05:00
Thomas Harte	180045ada6	Convert vram_access_delay into a free-standing function.	2023-01-01 13:51:52 -05:00
Thomas Harte	11542e7a7f	Improve const correctness, simplify inheritance.	2023-01-01 13:49:11 -05:00
Thomas Harte	71598250ea	Improve commentary.	2023-01-01 13:41:51 -05:00
Thomas Harte	ffb0b2ce0b	Eliminate runtime duplication of personality.	2022-12-31 21:50:57 -05:00
Thomas Harte	b7c315058f	Also template Base.	2022-12-31 21:47:05 -05:00
Thomas Harte	7d6eac2895	Template the TMS on its personality. ... Template parameter currently unused, but preparatory to other improvements.	2022-12-31 15:08:33 -05:00
Thomas Harte	d79aac3081	Shuffle the personality enum into the 'public' header.	2022-12-31 15:01:11 -05:00
Thomas Harte	8d5547dc9e	Minor further style improvements. ... ... as I refamiliarise myself.	2022-12-29 22:09:14 -05:00
Thomas Harte	5d89293c92	Improve constness, primarily of reverse_table.	2022-12-29 11:29:19 -05:00
Thomas Harte	711f7b2d75	C++17 makes this a single step.	2022-12-27 22:50:12 -05:00
Thomas Harte	dca8c51384	Prefer to avoid a macro.	2022-12-27 22:36:27 -05:00
Thomas Harte	462b7dcbfa	Add Mega Drive VRAM size.	2022-12-27 22:28:43 -05:00
Thomas Harte	2ab4b351ca	Extend enum.	2022-12-27 22:20:47 -05:00
Thomas Harte	99ced5476f	Add quick clock-rate notes.	2022-12-26 22:56:45 -05:00
Thomas Harte	fea8fecf11	Continue DMA requests if writing, even after a phase mismatch.	2022-09-15 16:46:22 -04:00
Thomas Harte	beca7a01c2	Treat a phase mismatch as ending DMA.	2022-09-15 16:34:06 -04:00
Thomas Harte	2d8e260671	Take a shot at the phase mismatch IRQ.	2022-09-15 16:24:06 -04:00
Thomas Harte	04f5d29ed9	Improve logging, factor out phase_matches per TODO comment.	2022-09-15 16:14:14 -04:00
Thomas Harte	df29a50738	Attempt to support the DMA interface.	2022-08-31 15:33:48 -04:00
Thomas Harte	ea4bf5f31a	Provide card's SCSI ID.	2022-08-23 15:05:36 -04:00
Thomas Harte	8f2e94a1d8	Switch name back to emphasise _async_.	2022-07-16 14:41:04 -04:00
Thomas Harte	bf03bda314	Generalise AsyncTaskQueue, DeferringAsyncTaskQueue and AsyncUpdater into a single template.	2022-07-14 16:39:26 -04:00
Thomas Harte	55af6681af	Avoid unnecessary get_port_input calls.	2021-11-24 17:15:48 -05:00
Thomas Harte	2a7a42ff8f	Add header for assert.	2021-11-24 16:28:18 -05:00
Thomas Harte	0ad1529f3f	Retain delegate bit length for non-self-clocked data.	2021-11-24 16:15:27 -05:00
Thomas Harte	0df8173536	Merge branch 'master' into Amiga	2021-11-24 08:58:03 -05:00
Thomas Harte	f5d3d6bcea	Splits the lowpass filter into push and pull variants.	2021-11-21 15:37:29 -05:00
Thomas Harte	4fc25fb798	Adds basic shift input.	2021-11-07 05:18:54 -08:00
Thomas Harte	941d9a46a2	Makes a better effort at exposition; better implements clocked line.	2021-11-07 05:18:40 -08:00
Thomas Harte	ecfe68d70f	Introduce the principle that a Serial::Line can be two-wire — clock + data.	2021-11-06 16:54:20 -07:00
Thomas Harte	f102d8a4b4	Extend to allow full-[byte/word/dword] writes, in LSB or MSB order.	2021-11-06 12:01:32 -07:00
Thomas Harte	6d34432988	Starts to build in a serial line for input.	2021-11-04 18:54:28 -07:00
Thomas Harte	b827b9e33e	Add necessary shift storage.	2021-11-03 19:26:45 -07:00
Thomas Harte	29e5ecc282	Add TODOs rather than complete stop on shift register acccesses.	2021-11-02 18:19:31 -07:00
Thomas Harte	9ecd43238f	Correct 8520 TOD setting and getting.	2021-10-30 12:02:43 -07:00
Thomas Harte	5ffe71346c	Eliminate interrupt magic constants.	2021-10-29 19:04:06 -07:00
Thomas Harte	d9d20d9d30	Walk back slightly.	2021-10-14 18:02:58 -07:00
Thomas Harte	689bfbbdb3	Be overt in initialiser list.	2021-10-14 16:57:26 -07:00
Thomas Harte	eb157f15f3	Adds index hole interrupt.	2021-10-09 04:08:59 -07:00
Thomas Harte	73e45511dc	Add missing #include.	2021-10-04 05:26:38 -07:00
Thomas Harte	e47eab1d40	Merge branch 'master' into Amiga	2021-09-14 20:27:59 -04:00
Thomas Harte	dfcd1508c9	Establishes valid initial BRAM.	2021-09-10 19:56:20 -04:00
Thomas Harte	0ca4631279	Switch to zero-initialised state; be more careful about resetting data.	2021-09-09 23:08:13 -04:00
Thomas Harte	a6221ca322	Reload data only if an output is found.	2021-09-09 22:07:03 -04:00
Thomas Harte	f8380d2d4c	Add 8250 feature of 'count, regardless'.	2021-08-08 22:32:41 -04:00
Thomas Harte	1f9e41e9cb	Ensure TOD isn't firing from power-on.	2021-08-08 18:51:58 -04:00
Thomas Harte	98bd6fc240	Adds a further logging hint.	2021-08-06 23:16:06 -04:00