12 Commits

Author	SHA1	Message	Date
Thomas Harte	d832e5e10d	Reduced 1540 PLL to running at 4Mhz. Which is possibly correct (?) Made minor change to avoid divide if possible.	2016-08-02 21:28:50 -04:00
Thomas Harte	5c1614ce7b	Attempted to simplify, very slightly.	2016-07-28 14:35:39 -04:00
Thomas Harte	015cea494d	Switched to a much-more straightforward PLL. I think I'm just fiddling now rather than moving forwards. Probably time to move on?	2016-07-28 11:32:14 -04:00
Thomas Harte	e061e849d4	Had a second bash at the PLL. Probably I should read some of the literature.	2016-07-27 16:24:24 -04:00
Thomas Harte	6afd619791	Eliminated floating point arithmetic.	2016-07-14 19:47:00 -04:00
Thomas Harte	6b4fec37ff	Moved down to a single divide.	2016-07-14 19:45:08 -04:00
Thomas Harte	481475a0f4	Switched to a full-on linear regression. Which causes the current tests to pass.	2016-07-14 19:42:01 -04:00
Thomas Harte	6d6b26b99f	Actually made things worse.	2016-07-14 07:32:27 -04:00
Thomas Harte	d8d3464c56	Made a quick-hack attempt at PLL synchronisation. Which doesn't work.	2016-07-14 07:31:23 -04:00
Thomas Harte	d1fe07f14d	Added test of perfect DPLL input timing.	2016-07-12 21:42:23 -04:00
Thomas Harte	94db45456e	Started sketching out the basic form here, albeit that it doesn't yet do _the only thing it advertises itself as useful for_.	2016-07-12 20:23:56 -04:00
Thomas Harte	75d95c0bc0	Sketched out an interface for a digial PLL. Not persuaded yet. Baby steps.	2016-07-11 22:12:58 -04:00