Thomas Harte
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e4d9022d37
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Returns deployment target to 10.13.
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2021-04-19 20:57:56 -04:00 |
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Thomas Harte
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572be48f38
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Attempts to add an early exit for non-Metal Macs.
This will be necessary only prior to 10.14.
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2021-04-19 20:55:25 -04:00 |
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Thomas Harte
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6f4ccebfa1
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Merge pull request #917 from TomHarte/InterruptAddress
Put the program counter on the bus during interrupt acknowledge.
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2021-04-19 20:08:22 -04:00 |
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Thomas Harte
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77fcf52d27
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Purely style: remove some redundant nullptrs.
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2021-04-19 18:53:00 -04:00 |
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Thomas Harte
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79c2bc1fd7
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Put the program counter on the bus during interrupt acknowledge.
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2021-04-19 18:43:50 -04:00 |
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Thomas Harte
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76370d9418
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Merge pull request #916 from TomHarte/OffByOne
Corrects off-by-one timing errors in the ZX Spectrum.
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2021-04-18 20:25:13 -04:00 |
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Thomas Harte
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7bac18bd65
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Address bus load time is not + 1/2.
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2021-04-18 18:41:24 -04:00 |
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Thomas Harte
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704737144a
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Corrects all interrupt timing for sign and off-by-one errors.
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2021-04-18 18:40:44 -04:00 |
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Thomas Harte
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2a9c73a1d3
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Merge pull request #915 from TomHarte/SpectrumSDLOptions
Adds display of Spectrum command-line options.
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2021-04-18 12:08:02 -04:00 |
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Thomas Harte
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e87e851401
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Add a redundant but idiomatic initial value.
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2021-04-18 11:56:22 -04:00 |
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Thomas Harte
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80d4846a27
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Respond with 0xff during an interrupt acknowledge.
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2021-04-18 11:56:00 -04:00 |
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Thomas Harte
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9fd53c9c91
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Adds the ZX Spectrum to ::AllMachines.
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2021-04-17 23:06:37 -04:00 |
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Thomas Harte
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53eae873d8
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Merge pull request #913 from TomHarte/LowerModelTiming
Brings timings into line with WoS specs.
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2021-04-16 22:45:54 -04:00 |
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Thomas Harte
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93422f4b1c
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Brings timings into line with WoS specs.
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2021-04-16 22:40:51 -04:00 |
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Thomas Harte
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06cedb2e50
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Merge pull request #912 from TomHarte/128kDecoding
Corrects Spectrum 128kb partial decoding.
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2021-04-16 22:02:25 -04:00 |
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Thomas Harte
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7fdb1d848b
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Corrects Spectrum 128kb partial decoding.
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2021-04-16 21:54:52 -04:00 |
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Thomas Harte
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246fd9442f
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Merge pull request #911 from TomHarte/48kbSpectrum
Adds the 48kb and 128kb Spectrums.
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2021-04-15 22:25:07 -04:00 |
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Thomas Harte
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eb99a64b29
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Adds new Spectrum models to Qt UI.
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2021-04-15 22:20:34 -04:00 |
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Thomas Harte
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d7954a4cb1
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Tweaks timing a little.
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2021-04-15 21:51:49 -04:00 |
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Thomas Harte
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ef636da866
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Attempts 48/128kb floating bus behaviour.
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2021-04-15 21:19:21 -04:00 |
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Thomas Harte
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fa18b06dbf
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Correct get_floating_value to be consistent in out-of-bounds behaviour.
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2021-04-15 21:13:36 -04:00 |
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Thomas Harte
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349b9ce502
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Don't post contended accesses other than on the +2a/+3.
Those machines have an actual latch for this stuff, the others don't.
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2021-04-15 21:13:06 -04:00 |
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Thomas Harte
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b2cf121410
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Regresses default to the more-compatible +2.
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2021-04-15 19:31:45 -04:00 |
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Thomas Harte
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71cf63bd35
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Corrects internal cycle contention.
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2021-04-15 19:17:11 -04:00 |
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Thomas Harte
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d1bb3aada4
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Attempts to complete the in-machine application of contention.
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2021-04-15 18:57:34 -04:00 |
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Thomas Harte
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b4214c6e08
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Blocks off the AY from inputs in 48kb mode.
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2021-04-15 18:04:16 -04:00 |
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Thomas Harte
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f5c7746493
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Extends fast loading support to the just-introduced models.
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2021-04-15 17:31:42 -04:00 |
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Thomas Harte
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f10ec80153
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Gets started on different video timings.
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2021-04-14 22:23:27 -04:00 |
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Thomas Harte
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0af405aa46
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Starts working in the 48kb and 128kb Spectrums.
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2021-04-14 21:37:10 -04:00 |
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Thomas Harte
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cf481effa6
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Merge pull request #910 from TomHarte/FastContention
Establishes that the 48/128kb contention patterns can be derived from my partial machine cycles alone.
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2021-04-14 20:21:52 -04:00 |
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Thomas Harte
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a1511f9600
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Establishes that the 48/128kb contention patterns can be derived from my partial machine cycles alone.
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2021-04-14 20:15:40 -04:00 |
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Thomas Harte
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325e2b3941
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Merge pull request #902 from TomHarte/Z80Lines
Spell out, test and correct Z80 bus activity.
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2021-04-13 22:22:26 -04:00 |
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Thomas Harte
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7017324d60
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r_step is obsolete now that I know that [DD/FD]CB don't have a refresh cycle.
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2021-04-13 22:17:30 -04:00 |
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Thomas Harte
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deb5d69ac7
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Consolidates macros.
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2021-04-13 22:11:28 -04:00 |
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Thomas Harte
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68a04f4e6a
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Adds IN/OUT I/D [R] to complete tests.
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2021-04-13 22:00:24 -04:00 |
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Thomas Harte
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0d61902b10
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Adds CP[I/D/IR/DR] tests.
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2021-04-13 20:03:11 -04:00 |
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Thomas Harte
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3eec210b30
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Adds LDI/LDD/LDIR/LDDR tests.
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2021-04-13 20:00:29 -04:00 |
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Thomas Harte
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5998f3b35b
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Corrects LD[I/D/IR/DR] timing.
Macro cleanup to come.
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2021-04-13 20:00:18 -04:00 |
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Thomas Harte
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869567fdd9
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Corrects EX (SP), HL breakdown.
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2021-04-13 19:45:48 -04:00 |
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Thomas Harte
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2e70b5eb9f
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Advances to EX (SP), HL, leaving only [LD/CP/IN/OT][I/D]{R}.
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2021-04-13 19:45:29 -04:00 |
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Thomas Harte
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8a3bfb8672
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Adds an IN/OUT test.
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2021-04-13 17:55:51 -04:00 |
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Thomas Harte
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06f1e64177
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Advances to IO.
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2021-04-12 21:41:20 -04:00 |
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Thomas Harte
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b42780173a
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Establishes that there really is no Read4 and Read4Pre distinction.
Will finish these unit tests, then clean up.
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2021-04-12 20:54:10 -04:00 |
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Thomas Harte
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36c8821c4c
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Reaches the halfway point in tests.
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2021-04-12 17:29:03 -04:00 |
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Thomas Harte
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947de2d54a
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Switches five-cycle read to a post hoc pause.
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2021-04-12 17:17:08 -04:00 |
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Thomas Harte
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9347fe5f44
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Advances to next failing test: LD (ii+n), n.
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2021-04-12 17:11:58 -04:00 |
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Thomas Harte
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e82367def3
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Switches to test-conformant behaviour for (IX/IY+n) opcode fetches.
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2021-04-11 23:01:00 -04:00 |
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Thomas Harte
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9cde7c12ba
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Shifts responsibility for refresh into the fetch-decode-execute sequence.
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2021-04-11 22:50:24 -04:00 |
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Thomas Harte
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015556cc91
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Switch (ii+n) to Read4Pre.
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2021-04-11 10:26:14 -04:00 |
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Thomas Harte
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47c5a243aa
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Restructures, the better to explore errors.
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2021-04-10 21:32:42 -04:00 |
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