Thomas Harte
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7135259cc1
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Sought to flesh out error conditions.
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2017-08-12 16:36:37 -04:00 |
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Thomas Harte
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4909325e79
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Implemented read deleted data.
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2017-08-12 13:01:17 -04:00 |
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Thomas Harte
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a4ee697ed1
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Quickie: head unload is scheduled only if the head is presently loaded.
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2017-08-12 12:53:45 -04:00 |
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Thomas Harte
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0f15a2f97f
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Relented: it actually looks like status bytes aren't per-drive. But each drive may fail at seeking individually. So that piece of state accumulates at the 8272 drive.
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2017-08-12 12:52:36 -04:00 |
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Thomas Harte
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89ace671a4
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Corrected unload time. Was 8000 times too short.
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2017-08-12 09:44:01 -04:00 |
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Thomas Harte
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e7db2a2f6d
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Sought to introduce head loading and unloading delays.
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2017-08-12 09:36:21 -04:00 |
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Thomas Harte
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ffb1a14ace
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Minor: clear status registers before a read data.
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2017-08-11 18:56:33 -04:00 |
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Thomas Harte
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e4f04d0977
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Merge branch 'master' into AYFidelity
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2017-08-11 14:41:08 -04:00 |
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Thomas Harte
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a5593bec79
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Threw in support for the light-pen trigger.
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2017-08-10 15:00:14 -04:00 |
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Thomas Harte
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a1e2646301
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Imposed counter size limits.
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2017-08-10 14:58:24 -04:00 |
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Thomas Harte
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6a6e5ae79c
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Forced users of the 6845 to be explicit about which type. So far with no effect.
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2017-08-10 12:28:57 -04:00 |
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Thomas Harte
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02d792c003
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Simplified logic slightly, avoiding repetition.
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2017-08-10 11:48:37 -04:00 |
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Thomas Harte
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be8e7a4144
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Eliminated false register aliasing, restricted register sizes and locked out reading and writing where appropriate.
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2017-08-10 11:22:30 -04:00 |
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Thomas Harte
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b1dbd7833a
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Merge branch 'master' into 6845Address
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2017-08-10 11:15:08 -04:00 |
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Thomas Harte
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a4c910f1de
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This appears to be a more accurate take on 6845 address advancement — it is necessary that character output has finished for the line address to be updated.
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2017-08-10 11:12:53 -04:00 |
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Thomas Harte
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2eed24e859
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Made an initial attempt at [a subset of] multi-sector reads.
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2017-08-10 11:11:26 -04:00 |
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Thomas Harte
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b11d142cff
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Switched to descriptive names.
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2017-08-08 20:35:41 -04:00 |
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Thomas Harte
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021ff8674e
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Added something for sense drive status.
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2017-08-08 20:30:54 -04:00 |
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Thomas Harte
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e3d1f4fe1e
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Subjectively, this might be more correct. It definitely prevents intermediate frequencies. More research required.
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2017-08-08 17:58:35 -04:00 |
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Thomas Harte
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3bdedfd749
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Improved comments.
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2017-08-08 07:44:46 -04:00 |
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Thomas Harte
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46278ff297
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Experimental: is this meant to be a compare-before-increment?
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2017-08-07 23:02:29 -04:00 |
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Thomas Harte
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390ecec3d9
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Added: now declines to pass on output if in input mode for ports A and B.
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2017-08-07 19:56:22 -04:00 |
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Thomas Harte
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41a30c147d
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Adjusted: invalid register selection simply deselects all registers.
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2017-08-07 19:51:36 -04:00 |
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Thomas Harte
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4709ae80cb
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Added port direction tests.
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2017-08-07 19:36:55 -04:00 |
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Thomas Harte
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7fbb455836
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Per the CPC test I'm checking, 0s should be returned for non-retained bits, not 1s.
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2017-08-07 19:07:12 -04:00 |
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Thomas Harte
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745afd217f
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The port input/output flags are now honoured; reading a port that is set as an output returns the current output value.
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2017-08-07 19:01:18 -04:00 |
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Thomas Harte
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47732ffb98
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Prevented the 8272 from overreading ID fields (and, by doing so, overrunning its internal buffer). Exposed the MFMController's CRC generator for inspection.
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2017-08-07 12:37:22 -04:00 |
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Thomas Harte
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d07f3216ab
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Added a broad phase on whether seeking is ongoing.
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2017-08-07 12:12:59 -04:00 |
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Thomas Harte
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68c73184b1
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Had failed to spot that by taking control of stepping at this level, the appropriate invalidate_tracks were not being sent.
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2017-08-07 10:36:53 -04:00 |
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Thomas Harte
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7f824d6494
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Ensured seeks and recalibrates end immediately if no seeking is required.
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2017-08-07 10:31:32 -04:00 |
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Thomas Harte
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3219212f03
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A closer inspection of the data sheet seems to suggest that invalid command sequences will post ST0.
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2017-08-07 07:35:41 -04:00 |
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Thomas Harte
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d90e35e5bd
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Added a bunch of comments, and ensured that the data request bit remains set for the entire period that command bytes are accepted.
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2017-08-07 07:27:00 -04:00 |
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Thomas Harte
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73f8488150
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Reaching the end of the usable part of my day, decided to tidy up a little before bed with indentation that reflects a distinction between top-level entry points and mere loops.
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2017-08-06 22:14:18 -04:00 |
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Thomas Harte
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3853966a1e
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Removed formal storage of ST3, as it just seems to be composed live. This may turn out also to be the best way to deal with ST0–2, time will tell. Also took a stab at the error in responding properly to the ROM's intended use of seek might be accepting new commands as replacements for old ones rather than rejecting them. That didn't seem to do the trick.
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2017-08-06 22:10:12 -04:00 |
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Thomas Harte
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d63893a437
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Collapsed implementations of recalibrate and seek, and decided to intend to go for an upward count on steps taken rather than a downward one. But seek continues presently to fail.
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2017-08-06 21:52:52 -04:00 |
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Thomas Harte
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90c74043f5
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Remembered to toggle off RQM between bytes. CAT now works.
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2017-08-06 21:21:59 -04:00 |
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Thomas Harte
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600445d90a
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Made a first attempt to return sector contents.
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2017-08-06 20:40:29 -04:00 |
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Thomas Harte
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e4b405fd3d
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With the ROM now using a read ID to set its expectations, implemented that and fixed FIND/READ_HEADER macros for multiple use. Execution now reaches the unimplemented section of read data.
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2017-08-06 20:32:46 -04:00 |
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Thomas Harte
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3b7ecbdf0d
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Renamed result_ to result_stack_ to emphasis the fact that it goes backwards. Switched meaning of CB so that it is set for the entire command, execution and result phases.
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2017-08-06 20:17:12 -04:00 |
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Thomas Harte
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01efb645cb
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Took a reasonable gamble that the CHRN reported is from internal registers, not from the last-found header.
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2017-08-06 19:57:34 -04:00 |
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Thomas Harte
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b5ec1f42d5
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Started resetting 'busy' when entering the result phase. AMSDOS now complains of a missing disk after failing to find sector 01. My belief is that it should end up asking for C1. So this is not even getting through a failure to find a sector correctly yet.
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2017-08-06 19:48:17 -04:00 |
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Thomas Harte
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e9972aa0dd
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Added respect for the index-hole limit on reading, and an error phase.
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2017-08-06 19:25:44 -04:00 |
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Thomas Harte
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1c9a744b01
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Made an effort to start inspecting ID fields, at least. Discovered that my emulation has somehow stopped proceeding beyond sense interrupt status though. Fix one in that area: adjust ST0 just in time for the sense interrupt status response, as that'll need to specify the drive number properly.
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2017-08-06 18:06:20 -04:00 |
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Thomas Harte
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e6d4bb29d8
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Discovered correct sense interrupt status result if nobody is in the completed seeking state, and switched to it. It's a single 0x80 rather than two bytes.
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2017-08-06 15:34:33 -04:00 |
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Thomas Harte
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6c5b562d97
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Made an attempt at some of the correct seek/recalibrate behaviour: it's now asynchronous from command processing and able to work on up to four drives at once. I just probably am not yet hitting all the status flags I need to hit.
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2017-08-06 15:22:07 -04:00 |
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Thomas Harte
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a7103f9333
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Disks are now communicated to the 8272. Which is able to handle four of them.
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2017-08-06 13:24:14 -04:00 |
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Thomas Harte
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c12425e141
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Added storage for the extended four status registers, and made an attempt at implementing the two most trivial result-phase commands. Am slightly paused momentarily trying to figure out whether seek activity is orthogonal to read/write activity.
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2017-08-06 12:55:57 -04:00 |
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Thomas Harte
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89f6de1383
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Started on a real ugly-implementation coroutine approach, and implemented specify as a fairly trivial first command: it has no result phase, and is the only thing called by AMSDOS as part of the initialisation sequence.
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2017-08-06 12:36:18 -04:00 |
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Thomas Harte
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34eaf75352
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Fixed WAIT_FOR_TIME macro.
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2017-08-06 12:08:54 -04:00 |
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Thomas Harte
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29288b690e
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Switched disk controllers to be instantiated explicitly in terms of cycles, created an Amstrad-specific subclass of the 8272 to record the direct programmatic availability of all disk motors bundled together, and otherwise adjusted to ensure the thing is clocked and that the motor is enabled and disabled appropriately. The 8272 is also now formally a subclass of the incoming MDM controller.
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2017-08-06 09:45:16 -04:00 |
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