Thomas Harte
e773b331cd
Implements register 2 listen.
2021-02-15 15:05:46 -05:00
Thomas Harte
99c21925f4
Makes attempt at keyboard mapping.
2021-02-15 15:00:12 -05:00
Thomas Harte
eccf5ca043
Makes first effort to wire up the ADB vertical blank input.
...
However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
2021-02-14 22:20:58 -05:00
Thomas Harte
24af62a3e5
Sets a default handler of 1.
2021-02-14 22:20:07 -05:00
Thomas Harte
52cf15c3e6
Attempts to route out modifier state.
2021-02-14 21:15:31 -05:00
Thomas Harte
a791680e6f
Implements set_status as per advice.
2021-02-14 21:04:20 -05:00
Thomas Harte
6e53b4c507
Corrects centralised ADB decoder.
...
I still think it's appropriate to do this in only a single place, given that using it is optional.
2021-02-14 20:41:05 -05:00
Thomas Harte
52c38e72f6
Starts seeking to automate register 3 handling.
...
Immediate pitfall: byte capture on the bus side isn't working correctly.
2021-02-14 20:37:33 -05:00
Thomas Harte
a51d143c35
Corrects reactive-device transmission logic.
...
Albeit that I'm still not properly responding to register 3 stuff, so the ADB bus needn't believe anything is out there. Also, without VSYNC being piped to the microcontroller it may well just not be polling anyway.
2021-02-14 18:54:22 -05:00
Thomas Harte
17e9305282
Starts adding a keyboard.
2021-02-13 23:16:45 -05:00
Thomas Harte
c284b34003
Resolves inability of ADB microcontroller to read its own ROM (!)
2021-02-13 17:53:40 -05:00
Thomas Harte
2ab3bba695
Attempts GLU register latching, restoring expected startup sequence.
2021-02-13 17:38:42 -05:00
Thomas Harte
2c4dcf8843
Edges towards implementing an ADB device.
2021-02-12 21:50:24 -05:00
Thomas Harte
ea40b2c982
Takes a stab at implementing device response.
2021-02-12 18:56:43 -05:00
Thomas Harte
adfdfa205f
Starts to establish the means by which I'll implement ADB devices.
2021-02-12 18:42:12 -05:00
Thomas Harte
33abdc95aa
Adds a helper for decoding ADB commands.
...
Still very noticeably to do: any sort of standard part for devices to respond to the bus.
2021-02-10 21:39:33 -05:00
Thomas Harte
6ca8aa99fc
Commit SDL and Qt project files; improve commenting.
2021-02-10 21:28:32 -05:00
Thomas Harte
17bac4c8cf
Starts to formalise the ADB bus.
2021-02-10 21:24:31 -05:00
Thomas Harte
46bd20b5e0
Attempts to simplify ADB bit parsing.
...
On-line output still looks reasonable, albeit that the microcontroller suddenly seems to be interested in devices F and 3 rather than 2 and 3.
2021-02-08 22:08:49 -05:00
Thomas Harte
93a80a30d3
With correct divider appears to get reset requests posted.
2021-02-07 23:05:01 -05:00
Thomas Harte
77b1efd176
Sets sensible 'reset' values.
2021-02-07 21:53:57 -05:00
Thomas Harte
acfab1dfb3
Starts to make some effort at timers.
2021-02-06 21:02:44 -05:00
Thomas Harte
6526c645a5
Merge branch 'master' into AppleIIgs
2021-02-02 21:29:38 -05:00
Thomas Harte
1e041f1adf
Flips conditionals to ensure 65802 safety.
2021-02-02 20:52:34 -05:00
Thomas Harte
beb514b231
Adds an additional mapping for copy.
2021-02-02 20:37:15 -05:00
Thomas Harte
f57e897085
Corrects visibility of SCSI output.
2021-02-02 20:24:39 -05:00
Thomas Harte
9f202d4238
Adds SCSI interrupt support.
2021-02-01 17:40:11 -05:00
Thomas Harte
1a40cc048e
Niceties: include AP6 ROM for hard-disk users; show SCSI activity indicator.
2021-01-31 21:41:11 -05:00
Thomas Harte
53514c7fdc
Ensures non-breakage of Qt interface.
2021-01-31 21:28:55 -05:00
Thomas Harte
274b3c7d24
Handles SCSI changes on-demand.
2021-01-31 21:24:54 -05:00
Thomas Harte
906b6ccdb7
This appears to be sufficient for the Electron to _read_ SCSI.
...
So that's step one.
2021-01-31 18:36:29 -05:00
Thomas Harte
8db289e229
Adds some notes-to-self on SCSI and a route to using Acorn's ADFS.
2021-01-31 13:12:59 -05:00
Thomas Harte
2860be7068
Permit a longer pause at startup for Electron commands that start with shift, control or func.
2021-01-31 12:25:22 -05:00
Thomas Harte
b5ecd5f7ef
Merge branch 'master' into AppleIIgs
2021-01-31 11:47:40 -05:00
Thomas Harte
4636d8dfb7
Adds support for installing the AP6 ROM and/or sideways RAM.
2021-01-30 19:38:19 -05:00
Thomas Harte
b8c6d4b153
Rips out my high-level ADB microcontroller protocol implementation.
...
Adds just enough that the main computer validates the ADB controller as present and talking.
2021-01-30 17:53:27 -05:00
Thomas Harte
f50e8b5106
If I'm going to maintain the max_address approach, & is 'correct'.
...
% +1 would be 'more correct', but I think this approach is probably misguided.
2021-01-27 18:31:11 -05:00
Thomas Harte
dcc2fe0990
Improves M50470 entry-point detection, adds test output.
2021-01-26 21:29:17 -05:00
Thomas Harte
56111c75ae
Makes first efforts towards disassembly.
2021-01-26 19:52:30 -05:00
Thomas Harte
fc4bda0047
Experimentally flipping interpretation of the output bit gives something closer to coherent.
2021-01-25 22:02:39 -05:00
Thomas Harte
c8beb59172
Attempts properly to track ADB bus activity.
...
Output is not yet a valid ADB stream. Work to do.
2021-01-25 17:43:22 -05:00
Thomas Harte
8789ffda15
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-24 22:30:42 -05:00
Thomas Harte
e8e604dc3c
Attempts to wire up M50470 and GLU.
...
Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 18:07:05 -05:00
Thomas Harte
57e0fdfadc
Ensures ADB microcontroller is clocked.
...
And runs at the 'correct' speed (i.e. modulo my instruction-by-instruction implementation).
2021-01-23 22:55:12 -05:00
Thomas Harte
ec0018df79
Routes in the ADB keyboard ROM. This should get as far as parsing.
2021-01-18 16:59:49 -05:00
Thomas Harte
12784a71e2
A stab in the dark: does the IOLC inhibit also affect vector fetches?
2020-12-29 20:53:56 -05:00
Thomas Harte
114d48b076
This register appears to be read/write.
2020-12-11 21:43:34 -05:00
Thomas Harte
6e9d517c26
Minor cleanliness improvement.
2020-12-11 21:43:13 -05:00
Thomas Harte
159924dcc0
More clarity tweaks.
2020-12-10 22:47:11 -05:00
Thomas Harte
5d8f284757
Makes minor style improvements.
2020-12-10 22:11:53 -05:00
