Thomas Harte
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fd1955e15b
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Attempt to randomise and test register contents.
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2022-06-08 15:12:47 -04:00 |
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Thomas Harte
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f4f93f4836
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Test a single, whole instruction; record read/write.
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2022-06-08 14:53:04 -04:00 |
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Thomas Harte
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dd0a7533ab
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Randomise all parts of memory other than the opcode.
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2022-06-08 14:43:51 -04:00 |
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Thomas Harte
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50130b7004
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Minor layout tweak.
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2022-06-08 11:42:42 -04:00 |
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Thomas Harte
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ab52c5cef2
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Pass first all-zeroes test, establishing that processors aren't being fully reset.
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2022-06-08 10:56:54 -04:00 |
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Thomas Harte
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c7fa93a5bc
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Attempt human-legible explanation of differences encountered.
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2022-06-08 10:51:05 -04:00 |
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Thomas Harte
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400b73b5a2
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Allow capture to be limited; retain timestamps.
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2022-06-08 09:49:27 -04:00 |
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Thomas Harte
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788b026cf5
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Log and attempt to compare some activity. Sort of.
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2022-06-07 16:56:05 -04:00 |
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Thomas Harte
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c4ae5d4c8d
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Establishes at least that both 68000s can run.
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2022-06-06 21:47:10 -04:00 |
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Thomas Harte
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ca8dd61045
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Start sketching out an old vs new 68000 test.
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2022-06-06 21:19:57 -04:00 |
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Thomas Harte
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7b3cf6e747
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Add missing instruction: RESET.
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2022-06-03 11:15:39 -04:00 |
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Thomas Harte
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640b04e59e
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Test only well-defined flags.
Albeit that timing is still off.
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2022-06-03 10:18:46 -04:00 |
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Thomas Harte
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10b9b13673
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Disable divide-by-zero PC test in lieu of better documentation.
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2022-06-03 08:27:20 -04:00 |
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Thomas Harte
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90d720ca28
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Don't test undocumented flags.
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2022-06-02 12:30:39 -04:00 |
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Thomas Harte
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6dd89eb0d7
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Adjust my expectation as to length.
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2022-06-02 12:11:54 -04:00 |
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Thomas Harte
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e1abf431cb
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Don't test undefined flags.
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2022-05-30 16:23:51 -04:00 |
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Thomas Harte
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8e0fa3bb5f
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DIV # with a divide by zero should be 44 cycles.
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2022-05-29 21:22:45 -04:00 |
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Thomas Harte
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9eea471e72
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Resolve infinite recursion.
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2022-05-29 20:39:22 -04:00 |
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Thomas Harte
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2a40e419fc
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Fix CHK tests: timing and expected flags.
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2022-05-29 15:26:56 -04:00 |
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Thomas Harte
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5f030edea4
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Simplify transaction.
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2022-05-26 19:37:30 -04:00 |
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Thomas Harte
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88e33353a1
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Fix instruction and time counting, and initial state.
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2022-05-26 09:17:37 -04:00 |
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Thomas Harte
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f3c0c62c79
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Switch register-setting interface.
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2022-05-26 07:52:14 -04:00 |
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Thomas Harte
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866787c5d3
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Make an effort to withdraw from the high-circuitous stuff of working around the reset sequence.
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2022-05-25 20:22:38 -04:00 |
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Thomas Harte
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64491525b4
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Work further to guess at caller's intention for set_state.
Probably I should just eliminate the initial reset, somehow.
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2022-05-25 17:01:18 -04:00 |
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Thomas Harte
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68b184885f
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Reapply only the status.
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2022-05-25 16:54:25 -04:00 |
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Thomas Harte
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06f3c716f5
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Make better effort to establish initial state.
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2022-05-25 16:47:41 -04:00 |
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Thomas Harte
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22714b8c7f
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Capture state at instruction end, for potential inspection.
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2022-05-25 16:32:26 -04:00 |
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Thomas Harte
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f9d1c554b7
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Fix for the actual number of cycles in a standard reset.
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2022-05-25 16:05:28 -04:00 |
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Thomas Harte
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f2a7660390
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Merge branch 'master' into 68000Mk2
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2022-05-25 15:40:10 -04:00 |
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Thomas Harte
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4961e39fb6
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Mention DIVU/DIVS flags.
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2022-05-25 15:39:00 -04:00 |
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Thomas Harte
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0bedf608c0
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Add details on gaps in coverage.
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2022-05-25 15:36:27 -04:00 |
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Thomas Harte
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1ab831f571
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Add the option to log a list of all untested instructions.
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2022-05-25 13:17:01 -04:00 |
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Thomas Harte
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2c6b9b4c9d
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Switch comparative trace tests to 68000 Mk2.
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2022-05-25 11:32:00 -04:00 |
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Thomas Harte
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463fbb07f9
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Adapt remaining 68000 tests to use Mk2.
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2022-05-25 10:55:17 -04:00 |
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Thomas Harte
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4b07c41df9
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Ensure alignment of storage.
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2022-05-24 11:29:28 -04:00 |
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Thomas Harte
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a87f6a28c9
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Fix LINK A7.
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2022-05-23 10:43:17 -04:00 |
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Thomas Harte
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98325325b1
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Fix UNLINK A7.
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2022-05-23 10:27:44 -04:00 |
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Thomas Harte
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26bf66e3f8
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Fix shifts and rolls.
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2022-05-23 10:09:46 -04:00 |
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Thomas Harte
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c6b3281274
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Attempt the shifts and rolls.
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2022-05-23 09:29:19 -04:00 |
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Thomas Harte
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1e8adc2bd9
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Fix MOVEP to R.
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2022-05-23 09:00:37 -04:00 |
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Thomas Harte
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c73021cf3c
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Implement MOVE.
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2022-05-23 08:46:06 -04:00 |
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Federico Berti
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1a26d4e409
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Update nbcd_pea.json
Add missing bracket
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2022-05-23 12:14:00 +01:00 |
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Thomas Harte
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269263eecf
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Implement RTE, RTS, RTR.
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2022-05-22 21:16:38 -04:00 |
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Thomas Harte
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4e21cdfc63
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Enable NEGX/CLR tests.
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2022-05-22 20:55:21 -04:00 |
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Thomas Harte
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faef5633f8
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Ensure MOVE from SR has an effective address to write to.
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2022-05-22 20:52:00 -04:00 |
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Thomas Harte
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7d1f1a3175
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Implement MOVE [to/from] [CCR/SR].
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2022-05-22 19:45:22 -04:00 |
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Thomas Harte
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4e34727195
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Fully implement TAS.
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2022-05-22 16:14:03 -04:00 |
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Thomas Harte
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1dd6ed6ae3
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Implement TAS Dn, with detour for other TASes.
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2022-05-22 16:08:30 -04:00 |
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Thomas Harte
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cb4d6710df
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Switch to a more direct indication of progress.
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2022-05-22 11:27:58 -04:00 |
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Thomas Harte
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284f23c6ea
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Implement JMP.
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2022-05-22 07:16:38 -04:00 |
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