 Adrian Conlon
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608fbb55fb
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Couple of small tidy ups
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2026-05-18 20:46:42 +01:00 |
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Adrian Conlon
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dfd4d1928f
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Make "Pop" more like "Read". i.e. don't return a result, just use the value placed on the "bus"
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2026-05-18 18:24:32 +01:00 |
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Adrian Conlon
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741feb4342
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Performance change: avoid dropping Bus.Data return values
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2026-05-18 17:28:41 +01:00 |
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Adrian Conlon
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b8e95f52b3
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Inline clock ticking mechanism
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2026-05-17 10:27:34 +01:00 |
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Adrian Conlon
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072a8dd984
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Blargg tests run again. Corrected speed issue of MemoryMappings being created too often and bus data being trashed by a write to ROM.
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2026-05-17 09:50:12 +01:00 |
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Adrian Conlon
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9a011b3c57
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Start implementing HD6309. Introduction of 32-bit operations has forced me to rename some of "Word" methods to better indicate size
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2026-05-16 21:10:23 +01:00 |
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Adrian Conlon
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ab835297fd
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Couple of small tidy ups
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2026-05-16 13:50:14 +01:00 |
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Adrian Conlon
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e0fffdaa5e
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Some performance improvements. About 50Mhz for Z80 emulator. 275Mhz to 325Mhz. Interesting.
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2026-05-16 11:09:03 +01:00 |
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Adrian Conlon
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ac200d7f76
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Simplify ignored return value handling
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2026-05-12 22:21:13 +01:00 |
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Adrian Conlon
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69a0865ee9
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Start work towards WDC 65C02 implementation
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2026-05-02 17:02:36 +01:00 |
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Adrian Conlon
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de12029c13
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Speedup Z80 by encouraging runtime inlining of code
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2026-04-20 18:56:05 +01:00 |
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Adrian Conlon
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699791f7a4
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Simplify intermediate 16-bit register usage
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2026-04-16 13:47:24 +01:00 |
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Adrian Conlon
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53e33b9eef
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Some simplifications
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2026-04-07 12:02:31 +01:00 |
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Adrian Conlon
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47baff3740
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Correct some 8080 timing mistakes
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2026-03-27 18:16:09 +00:00 |
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Adrian Conlon
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c587da19c4
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Interesting. At best agressive inlining had zero effect and may have slowed things down slightly
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2026-03-27 18:15:02 +00:00 |
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Adrian Conlon
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290f7583c5
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Correct region mis-label
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2026-03-27 18:14:24 +00:00 |
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Adrian Conlon
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a8ef9aa7db
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simplification and unification of build stuff
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2026-02-16 11:15:58 +00:00 |
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Adrian Conlon
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810d05a50e
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tidy the intel op-code decoder a little
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2025-11-27 16:49:44 +00:00 |
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Adrian Conlon
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1dfd9621a1
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Share some more common code between Intel style procesors
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2025-10-15 19:46:10 +01:00 |
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Adrian Conlon
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33fce45cc8
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Some performance updates
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2025-10-13 17:36:32 +01:00 |
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Adrian Conlon
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ceacac4741
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Fix up some oddities in the EightBit library
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2025-10-06 13:44:31 +01:00 |
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Adrian Conlon
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1779d1dc40
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Intel processors all seem to act slightly differently with regards to HALT
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2025-08-17 12:03:51 +01:00 |
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Adrian Conlon
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a4e704fef4
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I give up. This is probably more compatible with Intel derived processors
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2025-08-13 19:03:25 +01:00 |
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Adrian Conlon
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558da38f12
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Note commonality between Intel-style processors
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2025-08-10 12:43:34 +01:00 |
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Adrian Conlon
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e8a1e7dc6e
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Sort out Z80/Spectrum pin handling (again!)
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2025-08-08 21:47:48 +01:00 |
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Adrian Conlon
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41be64ad99
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Simplfy interrupts on Z80
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2025-08-07 19:05:41 +01:00 |
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Adrian Conlon
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d332c57e47
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Simplify Z80 port handling
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2025-08-07 09:56:25 +01:00 |
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Adrian Conlon
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ed6c7968bd
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Remove effectively impossible to use methods
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2025-08-07 09:42:23 +01:00 |
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Adrian Conlon
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796042acdf
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Simplfy intel processor interations
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2025-08-04 19:47:40 +01:00 |
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Adrian Conlon
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9d208de9bb
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Explicitly state order of operations in code, rather than relying upon RAII etc. (for speed. Much faster)
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2025-08-04 15:47:26 +01:00 |
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Adrian Conlon
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60ef099208
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Tidy some inconsistencies in various emulation
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2025-08-01 15:01:20 +01:00 |
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Adrian Conlon
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2f338c6c46
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Tidy register increment/decrement a little.
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2025-07-25 16:32:30 +01:00 |
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Adrian Conlon
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c271b28495
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Simplify bus addressing
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2025-07-05 09:46:59 +01:00 |
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Adrian Conlon
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3bbf300e05
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Simplify switching processor pin handling
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2025-06-22 21:07:02 +01:00 |
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 Adrian Conlon
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caca3467d9
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More unit test stuff. New tests generated by copilot
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2025-05-13 09:52:12 +01:00 |
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Adrian Conlon
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8331b4818e
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Couple of small Register16 adjustments
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2025-05-11 21:30:15 +01:00 |
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Adrian Conlon
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36e983526e
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Add increment/decrement operations to the Register16 class
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2025-05-11 19:24:40 +01:00 |
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Adrian Conlon
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d92926c15b
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Quite a fun low level rearrangement of the 16-bit register class.
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2025-05-08 19:46:08 +01:00 |
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Adrian Conlon
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9e0006187e
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Port access in Intel processors is 16 rather than 8 bit addressed
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2025-05-08 13:00:30 +01:00 |
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Adrian Conlon
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95783d37aa
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Reset/power refactoring for z80
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2025-05-06 15:37:24 +01:00 |
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Adrian Conlon
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d58095a9d0
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Power-on and reset consistency fixes
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2025-05-06 11:52:33 +01:00 |
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Adrian Conlon
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93e09c192f
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Share instruction fetch and halt implementations
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2025-05-04 11:41:28 +01:00 |
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Adrian Conlon
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2336222c97
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Push more core processor handling into base classes.
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2025-05-04 10:53:23 +01:00 |
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Adrian Conlon
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e4494e943a
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PC only proceeds when HALT pin is raised
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2025-05-04 00:36:01 +01:00 |
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Adrian Conlon
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cbe871d365
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Isolate program counter increment/decrement (to be used for HALT processing)
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2025-05-03 23:25:06 +01:00 |
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Adrian Conlon
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080f203a55
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Unify Intel style JR CC code and fix SM83 timing issues.
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2025-05-03 12:09:34 +01:00 |
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Adrian Conlon
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898a2bc7ea
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Try to bring the Z80 fusetest back to life
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2025-05-03 02:09:31 +01:00 |
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Adrian Conlon
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e1aa220409
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Further Z80 timing fixes: 290 failures
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2025-05-03 00:09:19 +01:00 |
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Adrian Conlon
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07330cc9c8
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Move a routine into a slightly better place
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2025-05-02 10:52:06 +01:00 |
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Adrian Conlon
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dd1d141f15
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Simplify conditional flag handling in intel processors
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2025-04-29 12:27:39 +01:00 |
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