 Adrian Conlon
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37fc258d47
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Some simplifications
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2026-05-21 11:57:52 +01:00 |
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Adrian Conlon
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608fbb55fb
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Couple of small tidy ups
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2026-05-18 20:46:42 +01:00 |
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Adrian Conlon
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dfd4d1928f
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Make "Pop" more like "Read". i.e. don't return a result, just use the value placed on the "bus"
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2026-05-18 18:24:32 +01:00 |
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Adrian Conlon
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741feb4342
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Performance change: avoid dropping Bus.Data return values
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2026-05-18 17:28:41 +01:00 |
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Adrian Conlon
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9a011b3c57
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Start implementing HD6309. Introduction of 32-bit operations has forced me to rename some of "Word" methods to better indicate size
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2026-05-16 21:10:23 +01:00 |
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Adrian Conlon
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e0fffdaa5e
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Some performance improvements. About 50Mhz for Z80 emulator. 275Mhz to 325Mhz. Interesting.
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2026-05-16 11:09:03 +01:00 |
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Adrian Conlon
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ac200d7f76
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Simplify ignored return value handling
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2026-05-12 22:21:13 +01:00 |
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Adrian Conlon
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de12029c13
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Speedup Z80 by encouraging runtime inlining of code
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2026-04-20 18:56:05 +01:00 |
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Adrian Conlon
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699791f7a4
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Simplify intermediate 16-bit register usage
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2026-04-16 13:47:24 +01:00 |
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Adrian Conlon
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47baff3740
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Correct some 8080 timing mistakes
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2026-03-27 18:16:09 +00:00 |
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Adrian Conlon
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a8ef9aa7db
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simplification and unification of build stuff
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2026-02-16 11:15:58 +00:00 |
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Adrian Conlon
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1dfd9621a1
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Share some more common code between Intel style procesors
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2025-10-15 19:46:10 +01:00 |
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Adrian Conlon
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ceacac4741
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Fix up some oddities in the EightBit library
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2025-10-06 13:44:31 +01:00 |
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Adrian Conlon
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1779d1dc40
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Intel processors all seem to act slightly differently with regards to HALT
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2025-08-17 12:03:51 +01:00 |
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Adrian Conlon
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a4e704fef4
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I give up. This is probably more compatible with Intel derived processors
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2025-08-13 19:03:25 +01:00 |
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Adrian Conlon
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558da38f12
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Note commonality between Intel-style processors
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2025-08-10 12:43:34 +01:00 |
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Adrian Conlon
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e8a1e7dc6e
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Sort out Z80/Spectrum pin handling (again!)
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2025-08-08 21:47:48 +01:00 |
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Adrian Conlon
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41be64ad99
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Simplfy interrupts on Z80
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2025-08-07 19:05:41 +01:00 |
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Adrian Conlon
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796042acdf
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Simplfy intel processor interations
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2025-08-04 19:47:40 +01:00 |
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Adrian Conlon
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9d208de9bb
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Explicitly state order of operations in code, rather than relying upon RAII etc. (for speed. Much faster)
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2025-08-04 15:47:26 +01:00 |
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Adrian Conlon
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2f338c6c46
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Tidy register increment/decrement a little.
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2025-07-25 16:32:30 +01:00 |
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Adrian Conlon
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c271b28495
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Simplify bus addressing
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2025-07-05 09:46:59 +01:00 |
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Adrian Conlon
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3bbf300e05
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Simplify switching processor pin handling
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2025-06-22 21:07:02 +01:00 |
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 Adrian Conlon
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36e983526e
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Add increment/decrement operations to the Register16 class
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2025-05-11 19:24:40 +01:00 |
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Adrian Conlon
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95783d37aa
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Reset/power refactoring for z80
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2025-05-06 15:37:24 +01:00 |
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Adrian Conlon
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d58095a9d0
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Power-on and reset consistency fixes
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2025-05-06 11:52:33 +01:00 |
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Adrian Conlon
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93e09c192f
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Share instruction fetch and halt implementations
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2025-05-04 11:41:28 +01:00 |
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Adrian Conlon
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2336222c97
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Push more core processor handling into base classes.
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2025-05-04 10:53:23 +01:00 |
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Adrian Conlon
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e4494e943a
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PC only proceeds when HALT pin is raised
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2025-05-04 00:36:01 +01:00 |
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Adrian Conlon
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080f203a55
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Unify Intel style JR CC code and fix SM83 timing issues.
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2025-05-03 12:09:34 +01:00 |
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Adrian Conlon
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07330cc9c8
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Move a routine into a slightly better place
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2025-05-02 10:52:06 +01:00 |
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Adrian Conlon
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dd1d141f15
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Simplify conditional flag handling in intel processors
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2025-04-29 12:27:39 +01:00 |
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Adrian Conlon
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1b1b92ac2c
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More event handling simplification
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2025-03-29 13:18:54 +00:00 |
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Adrian Conlon
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3d6b549c76
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Turns out using lambdas to control pins is lovely and correct, but terribly slow. Back to a more traditional method.
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2025-03-24 20:18:04 +00:00 |
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Adrian Conlon
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8a68fc5856
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Library fixes
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2025-03-18 21:32:44 +00:00 |
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Adrian Conlon
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fa13852e53
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Sort out GB timing (enough to pass Blargg, anyway)
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2024-10-12 14:38:45 +01:00 |
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Adrian Conlon
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691b800d1a
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More .net 9 analysis changes
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2024-10-12 12:24:42 +01:00 |
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Adrian Conlon
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9aa25fed7e
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Apply all analysis suggestions
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2024-10-12 09:14:29 +01:00 |
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Adrian Conlon
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d5c0dcc175
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Correct style issues
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2024-10-09 20:05:37 +01:00 |
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Adrian Conlon
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ee584867c2
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Modernise some more c# code
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2024-07-18 11:38:02 +01:00 |
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Adrian Conlon
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d80f340081
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Simplfy access to Z80 registers
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2024-07-04 08:47:53 +01:00 |
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Adrian Conlon
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0c8ed57b0d
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Add easy to use Register16 assignment methods
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2024-07-01 23:27:35 +01:00 |
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Adrian Conlon
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d8fad7b988
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Try to minimise use of "Word" from Register16
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2024-06-30 12:30:07 +01:00 |
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Adrian Conlon
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e0235f396e
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IDE suggestions
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2024-05-19 09:07:20 +01:00 |
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Adrian Conlon
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47ecdad3e8
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Work towards accurate bus/memory/io timings. Especially Z80 m-cycle timing.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2020-07-05 00:09:51 +01:00 |
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Adrian Conlon
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cd4af67177
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Work my way through a bunch of the analysis suggestions.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2020-06-22 00:00:15 +01:00 |
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Adrian Conlon
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aca81384c3
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Correct PC power on value issue.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-09-07 11:16:03 +01:00 |
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Adrian Conlon
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f01e3e0430
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Tighten up the sequence associated with changing pin levels + fix persistent HALT/PC bug
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-09-06 22:50:21 +01:00 |
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Adrian Conlon
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bc491884b0
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Synchronise HALT implementation for Intel style processors with the C++ version.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-08-29 09:05:31 +01:00 |
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Adrian Conlon
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84284d62b5
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Fuse fixes: Correct JR cc from unnecessary extra read of offset.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-08-15 14:30:12 +01:00 |
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