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a8ef9aa7dbc1932e62b506a1c8a5931a3ede158b
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54 Commits

Author SHA1 Message Date
Adrian Conlon
a8ef9aa7db simplification and unification of build stuff 2026-02-16 11:15:58 +00:00
Adrian Conlon
1dfd9621a1 Share some more common code between Intel style procesors 2025-10-15 19:46:10 +01:00
Adrian Conlon
ceacac4741 Fix up some oddities in the EightBit library 2025-10-06 13:44:31 +01:00
Adrian Conlon
1779d1dc40 Intel processors all seem to act slightly differently with regards to HALT 2025-08-17 12:03:51 +01:00
Adrian Conlon
a4e704fef4 I give up. This is probably more compatible with Intel derived processors 2025-08-13 19:03:25 +01:00
Adrian Conlon
558da38f12 Note commonality between Intel-style processors 2025-08-10 12:43:34 +01:00
Adrian Conlon
e8a1e7dc6e Sort out Z80/Spectrum pin handling (again!) 2025-08-08 21:47:48 +01:00
Adrian Conlon
41be64ad99 Simplfy interrupts on Z80 2025-08-07 19:05:41 +01:00
Adrian Conlon
796042acdf Simplfy intel processor interations 2025-08-04 19:47:40 +01:00
Adrian Conlon
9d208de9bb Explicitly state order of operations in code, rather than relying upon RAII etc. (for speed. Much faster) 2025-08-04 15:47:26 +01:00
Adrian Conlon
2f338c6c46 Tidy register increment/decrement a little. 2025-07-25 16:32:30 +01:00
Adrian Conlon
c271b28495 Simplify bus addressing 2025-07-05 09:46:59 +01:00
Adrian Conlon
3bbf300e05 Simplify switching processor pin handling 2025-06-22 21:07:02 +01:00
Adrian Conlon
36e983526e Add increment/decrement operations to the Register16 class 2025-05-11 19:24:40 +01:00
Adrian Conlon
95783d37aa Reset/power refactoring for z80 2025-05-06 15:37:24 +01:00
Adrian Conlon
d58095a9d0 Power-on and reset consistency fixes 2025-05-06 11:52:33 +01:00
Adrian Conlon
93e09c192f Share instruction fetch and halt implementations 2025-05-04 11:41:28 +01:00
Adrian Conlon
2336222c97 Push more core processor handling into base classes. 2025-05-04 10:53:23 +01:00
Adrian Conlon
e4494e943a PC only proceeds when HALT pin is raised 2025-05-04 00:36:01 +01:00
Adrian Conlon
080f203a55 Unify Intel style JR CC code and fix SM83 timing issues. 2025-05-03 12:09:34 +01:00
Adrian Conlon
07330cc9c8 Move a routine into a slightly better place 2025-05-02 10:52:06 +01:00
Adrian Conlon
dd1d141f15 Simplify conditional flag handling in intel processors 2025-04-29 12:27:39 +01:00
Adrian Conlon
1b1b92ac2c More event handling simplification 2025-03-29 13:18:54 +00:00
Adrian Conlon
3d6b549c76 Turns out using lambdas to control pins is lovely and correct, but terribly slow. Back to a more traditional method. 2025-03-24 20:18:04 +00:00
Adrian Conlon
8a68fc5856 Library fixes 2025-03-18 21:32:44 +00:00
Adrian Conlon
fa13852e53 Sort out GB timing (enough to pass Blargg, anyway) 2024-10-12 14:38:45 +01:00
Adrian Conlon
691b800d1a More .net 9 analysis changes 2024-10-12 12:24:42 +01:00
Adrian Conlon
9aa25fed7e Apply all analysis suggestions 2024-10-12 09:14:29 +01:00
Adrian Conlon
d5c0dcc175 Correct style issues 2024-10-09 20:05:37 +01:00
Adrian Conlon
ee584867c2 Modernise some more c# code 2024-07-18 11:38:02 +01:00
Adrian Conlon
d80f340081 Simplfy access to Z80 registers 2024-07-04 08:47:53 +01:00
Adrian Conlon
0c8ed57b0d Add easy to use Register16 assignment methods 2024-07-01 23:27:35 +01:00
Adrian Conlon
d8fad7b988 Try to minimise use of "Word" from Register16 2024-06-30 12:30:07 +01:00
Adrian Conlon
e0235f396e IDE suggestions 2024-05-19 09:07:20 +01:00
Adrian Conlon
47ecdad3e8 Work towards accurate bus/memory/io timings. Especially Z80 m-cycle timing. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2020-07-05 00:09:51 +01:00
Adrian Conlon
cd4af67177 Work my way through a bunch of the analysis suggestions. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2020-06-22 00:00:15 +01:00
Adrian Conlon
aca81384c3 Correct PC power on value issue. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-09-07 11:16:03 +01:00
Adrian Conlon
f01e3e0430 Tighten up the sequence associated with changing pin levels + fix persistent HALT/PC bug 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-09-06 22:50:21 +01:00
Adrian Conlon
bc491884b0 Synchronise HALT implementation for Intel style processors with the C++ version. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-08-29 09:05:31 +01:00
Adrian Conlon
84284d62b5 Fuse fixes: Correct JR cc from unnecessary extra read of offset. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-08-15 14:30:12 +01:00
Adrian Conlon
1d976e811d Introduce a little consistency with regards to pin naming and usage. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2019-04-23 00:58:33 +01:00
Adrian Conlon
e80963260d Try to avoid copying around Register16 references, if possible. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-03-07 01:21:00 +00:00
Adrian Conlon
03caba99dc Follow most of the guideline suggestions from VS2019 preview. Pretty good suggestions! 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-02-22 22:33:51 +00:00
Adrian Conlon
28b7a88f0f Use the correct virtual methods: BusRead and BusWrite to control bus access for Z80 a la M6502 implementation. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-02-22 19:59:42 +00:00
Adrian Conlon
27e1c5c9f8 Make Register16 a class, rather than struct. Tricky, but a bit faster than before. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-02-21 19:58:49 +00:00
Adrian Conlon
a144cf19a1 Whoops: missed bus read/write clock ticks in the 6502 emulator. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-02-18 00:52:45 +00:00
Adrian Conlon
ea82c58777 Add Z80 processor (untested, but complete) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-02-16 21:32:34 +00:00
Adrian Conlon
c6a7003b8d Help out callers using Register16 arguments a little: Don't always require the ".Word" property to be passed. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-02-15 00:26:01 +00:00
Adrian Conlon
63db46a7bc Resurrect the Register16 class. This (or something *very* much like it) is going to be necessary to add a Z80 emulator (reference access to the high/low parts of 16-bit registers). 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-02-14 23:01:31 +00:00
Adrian Conlon
0e8a530573 More analysis suggested tidy ups. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-02-06 23:41:56 +00:00