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• fc2b0470a3 Remove test patterns Adrian Conlon 2025-05-08 22:01:19 +01:00
• 19c18445d6 Remove a couple of pointless "Word"isms Adrian Conlon 2025-05-08 19:46:43 +01:00
• d92926c15b Quite a fun low level rearrangement of the 16-bit register class. Adrian Conlon 2025-05-08 19:46:08 +01:00
• 9e0006187e Port access in Intel processors is 16 rather than 8 bit addressed Adrian Conlon 2025-05-08 13:00:30 +01:00
• eda9519068 Correct some analysis issues Adrian Conlon 2025-05-07 21:30:19 +01:00
• 79c15602eb Small refactor Adrian Conlon 2025-05-07 21:27:01 +01:00
• 293c735ec5 Simplify indirect memory access Adrian Conlon 2025-05-07 11:56:23 +01:00
• 1a09473b5a Read port refactoring Adrian Conlon 2025-05-06 23:05:51 +01:00
• a6051a64ab More IO simplifications Adrian Conlon 2025-05-06 22:51:30 +01:00
• 62f42ef46f Refactored a little, but no functional changes Adrian Conlon 2025-05-06 21:41:32 +01:00
• db1da4f506 Remove extra line Adrian Conlon 2025-05-06 21:39:47 +01:00
• 95783d37aa Reset/power refactoring for z80 Adrian Conlon 2025-05-06 15:37:24 +01:00
• d58095a9d0 Power-on and reset consistency fixes Adrian Conlon 2025-05-06 11:52:33 +01:00
• e1696721f6 Simplifications and refactorings in th intel processors Adrian Conlon 2025-05-05 21:06:39 +01:00
• 37431d08bc Correct LD?R/CP?R block methods. 4 problem instuctions now. Adrian Conlon 2025-05-04 17:47:19 +01:00
• 045907e273 Fix INI/IND flag handling. 8 problems remaining Adrian Conlon 2025-05-04 17:22:23 +01:00
• 6d84c3a41f Get SCF/CCF X/Y flags working correctly. 10 problems reported now. Adrian Conlon 2025-05-04 16:00:08 +01:00
• 93e09c192f Share instruction fetch and halt implementations Adrian Conlon 2025-05-04 11:41:28 +01:00
• 2336222c97 Push more core processor handling into base classes. Adrian Conlon 2025-05-04 10:53:23 +01:00
• 47374e591d With my correct implementation of HALT, I need the fetch to take place during a halted state Adrian Conlon 2025-05-04 08:56:22 +01:00
• e4494e943a PC only proceeds when HALT pin is raised Adrian Conlon 2025-05-04 00:36:01 +01:00
• 853569b2ca Isolate REFRESH pin functionality Adrian Conlon 2025-05-04 00:35:14 +01:00
• cbe871d365 Isolate program counter increment/decrement (to be used for HALT processing) Adrian Conlon 2025-05-03 23:25:06 +01:00
• 2501bdfd28 More block timing issues corrected. 16 issues remaining Adrian Conlon 2025-05-03 22:46:02 +01:00
• 6d8a00876f Fix a bunch of "block" instruction timings. 16 problems remaining. Adrian Conlon 2025-05-03 19:51:36 +01:00
• a0d45eace1 Fix display of registers (from alternate set) when viewing z80 problems Adrian Conlon 2025-05-03 19:18:03 +01:00
• 26457b4a77 Correct timing for 16-bit arithmetic tests. 26 failures remaining Adrian Conlon 2025-05-03 15:03:04 +01:00
• 68328d92fb Fix displaced timing on arithmetic operations for z80. 34 failures now Adrian Conlon 2025-05-03 14:40:38 +01:00
• 506e2b9eda Fix some displaced memory load timing issues. 50 issues remaining. Adrian Conlon 2025-05-03 14:10:18 +01:00
• f9754dd62f Fix some z80 eight-bit load timing issues. 58 issues remaining Adrian Conlon 2025-05-03 13:54:18 +01:00
• 9f2079efae More z80 timing issues fixed. 70 issues remain Adrian Conlon 2025-05-03 13:21:36 +01:00
• 080f203a55 Unify Intel style JR CC code and fix SM83 timing issues. Adrian Conlon 2025-05-03 12:09:34 +01:00
• 0679b95b77 Correct LR35902 HALT test. Whatever problems this has, won't be solved by a hack Adrian Conlon 2025-05-03 11:58:57 +01:00
• 94b8da456b Fix loads of z80 timing issues. 84 timing issues remain. Adrian Conlon 2025-05-03 11:45:55 +01:00
• 898a2bc7ea Try to bring the Z80 fusetest back to life Adrian Conlon 2025-05-03 02:09:31 +01:00
• 946121defb Fix HALT instruction Adrian Conlon 2025-05-03 02:08:52 +01:00
• 561483d65d More timing fixes. 255 timing errors Adrian Conlon 2025-05-03 01:31:44 +01:00
• f4f4357a3e More z80 timing fixes, 261 errors Adrian Conlon 2025-05-03 00:51:20 +01:00
• e1aa220409 Further Z80 timing fixes: 290 failures Adrian Conlon 2025-05-03 00:09:19 +01:00
• 175069d6bf More Z80 timing fixes Adrian Conlon 2025-05-02 20:18:04 +01:00
• 3617608e8c Fix a number of write timing issues Adrian Conlon 2025-05-02 17:46:33 +01:00
• fda52af260 Only DJNZ has the extra tick (presumably to decrement the B register) Adrian Conlon 2025-05-02 14:07:15 +01:00
• 935466ad6f Correct timing issues both conditional and unconditional relative jumpson Z80 Adrian Conlon 2025-05-02 14:03:15 +01:00
• 9670c3fd21 Start correcting timing issues in my Z80 implementation Adrian Conlon 2025-05-02 12:11:54 +01:00
• 07330cc9c8 Move a routine into a slightly better place Adrian Conlon 2025-05-02 10:52:06 +01:00
• 5bae07ff8d Add single stepping Z80 testing code Adrian Conlon 2025-05-02 10:50:49 +01:00
• dd1d141f15 Simplify conditional flag handling in intel processors Adrian Conlon 2025-04-29 12:27:39 +01:00
• 973590690c Fix a bunch of analysis issues Adrian Conlon 2025-04-01 09:32:29 +01:00
• 820fb707b9 Update to latest EightBit library Adrian Conlon 2025-03-29 14:38:36 +00:00
• 1b1b92ac2c More event handling simplification Adrian Conlon 2025-03-29 13:18:54 +00:00
• b461eb97d6 Prefer to use events directly, rather than through "On" methods Adrian Conlon 2025-03-29 11:31:47 +00:00
• 87abbaa75e Tidy IO page access Adrian Conlon 2025-03-28 14:50:53 +00:00
• fa48a64cac Take advantage of some simplifications Adrian Conlon 2025-03-28 09:17:09 +00:00
• 3a9e89f009 Tidy a couple of IO effects in the LR35902 core Adrian Conlon 2025-03-28 09:03:32 +00:00
• 4d0059ad94 Only 7 failing instructions now Adrian Conlon 2025-03-27 14:34:54 +00:00
• 4db203de48 All interrupt handling state tests to work Adrian Conlon 2025-03-27 11:13:41 +00:00
• e3258846a8 Whoops: missed addition of SM83 tests to solution. Adrian Conlon 2025-03-27 10:19:59 +00:00
• 3ca3d60caf Correct some timing issues in GB core Adrian Conlon 2025-03-27 10:19:18 +00:00
• 08089823c2 First stab at getting LR35902 HarteTests running. Not bad, so far! Adrian Conlon 2025-03-26 21:16:37 +00:00
• 3d6b549c76 Turns out using lambdas to control pins is lovely and correct, but terribly slow. Back to a more traditional method. Adrian Conlon 2025-03-24 20:18:04 +00:00
• d4dc99b454 Use lambda functions to simplify CPU pin control Adrian Conlon 2025-03-23 11:08:36 +00:00
• 8a68fc5856 Library fixes Adrian Conlon 2025-03-18 21:32:44 +00:00
• a9db2f58bd miscellaneous fixes, especiall flags Adrian Conlon 2025-03-18 18:38:47 +00:00
• 21770b2460 Take some analysis suggestions Adrian Conlon 2025-02-23 12:14:30 +00:00
• 4676ea669a Simplification, but no fixes Adrian Conlon 2025-02-13 12:35:49 +00:00
• e8d770c6bb Simplify i/o port handling in Z80 implementation Adrian Conlon 2025-01-27 21:23:47 +00:00
• a15cff4588 Fix compilation problem Adrian Conlon 2025-01-26 21:57:05 +00:00
• f31442511f LR35902 analysis suggestions Adrian Conlon 2025-01-26 21:17:07 +00:00
• 1b8925ebe4 Remove extra blank line Adrian Conlon 2024-10-14 11:24:09 +01:00
• 4b4181e12d Synchonise with unmanaged GB implementation Adrian Conlon 2024-10-14 11:04:51 +01:00
• fa13852e53 Sort out GB timing (enough to pass Blargg, anyway) Adrian Conlon 2024-10-12 14:38:45 +01:00
• 0bc3cb9d03 first round of .net 9 analysis Adrian Conlon 2024-10-12 13:15:14 +01:00
• b38462bddf .net 9 gb analysis changes Adrian Conlon 2024-10-12 12:57:38 +01:00
• 4839f3fc04 .net 9 analysis Adrian Conlon 2024-10-12 12:26:21 +01:00
• 691b800d1a More .net 9 analysis changes Adrian Conlon 2024-10-12 12:24:42 +01:00
• f6829f2ec0 Z80 .net 9 analysis changes Adrian Conlon 2024-10-12 12:09:22 +01:00
• 3b80ee7b37 Shared test harness Adrian Conlon 2024-10-12 11:48:54 +01:00
• b1b050b1d3 .net 9 analysis changes Adrian Conlon 2024-10-12 11:09:29 +01:00
• c0a964fadb .net 9 analysis Adrian Conlon 2024-10-12 10:52:47 +01:00
• 515c679e68 Apply .net 9 analysis Adrian Conlon 2024-10-12 10:20:29 +01:00
• a3fd5b055a .net 9 Analysis Adrian Conlon 2024-10-12 09:55:05 +01:00
• f525fcf412 Apply .net 9 analysis changes Adrian Conlon 2024-10-12 09:44:39 +01:00
• 312316f61f Apply all .net 9 analysis suggestions Adrian Conlon 2024-10-12 09:28:05 +01:00
• 9aa25fed7e Apply all analysis suggestions Adrian Conlon 2024-10-12 09:14:29 +01:00
• 3d9b0aac56 Update to .Net 9 Adrian Conlon 2024-10-12 08:49:47 +01:00
• 0d695a6d7a Tidy up test harnesses Adrian Conlon 2024-10-10 11:27:31 +01:00
• 5c71acc40a More analysis code changes Adrian Conlon 2024-10-10 00:11:55 +01:00
• 4cd689350e More analsys changes Adrian Conlon 2024-10-09 22:47:37 +01:00
• 3cbc7f32d2 More analysis fixes Adrian Conlon 2024-10-09 22:46:25 +01:00
• 4190943998 Update code analysis/style settings Adrian Conlon 2024-10-09 22:16:40 +01:00
• f0815d4150 Code analysis corrections. Adrian Conlon 2024-10-09 22:15:25 +01:00
• 647be6f224 More style changes Adrian Conlon 2024-10-09 21:16:55 +01:00
• d5c0dcc175 Correct style issues Adrian Conlon 2024-10-09 20:05:37 +01:00
• dc677e5358 Namespace tidying Adrian Conlon 2024-10-09 19:48:33 +01:00
• ed4b4e3736 Flatten symbols namespace Adrian Conlon 2024-10-07 19:34:48 +01:00
• 8d9e603165 Simplify section parsing Adrian Conlon 2024-10-07 19:23:12 +01:00
• 297f3b8dff Make the intel hex file format parser easier to use. Adrian Conlon 2024-10-07 09:40:26 +01:00
• b6043c3659 Whoops! Avoid joined test harness output Adrian Conlon 2024-10-06 15:56:05 +01:00
• 591290c3f5 Refactor section entry extraction for clarity Adrian Conlon 2024-10-06 15:55:04 +01:00
• ffe559d792 Add some simplifications for argument null exception handling Adrian Conlon 2024-10-06 13:24:04 +01:00