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• ac200d7f76 Simplify ignored return value handling Adrian Conlon 2026-05-12 22:21:13 +01:00
• a98b904207 Whoops: missed one more test Adrian Conlon 2026-05-12 22:19:11 +01:00
• f1fb442f08 Add 6809 Schwotzer tests Adrian Conlon 2026-05-12 22:18:51 +01:00
• b228332e27 Tidy up old debugging changes Adrian Conlon 2026-05-12 20:23:42 +01:00
• 96eaf1b22f Update interrupt timing Adrian Conlon 2026-05-12 15:23:45 +01:00
• 75a07ceea0 Add a little more documentation Adrian Conlon 2026-05-12 11:45:41 +01:00
• 83ee80edcf Make addressing mode handling more consistent on 6502 implementation Adrian Conlon 2026-05-12 11:44:42 +01:00
• d7e3ea0ef3 Use underscored private member variables Adrian Conlon 2026-05-11 23:07:34 +01:00
• fc1ad39a8d Add half-carry tests Adrian Conlon 2026-05-11 22:27:30 +01:00
• 37ed8b4d11 Increment shouldn't affect the half-carry flag Adrian Conlon 2026-05-11 22:20:10 +01:00
• 9f62175e06 Enhance "TST" tests Adrian Conlon 2026-05-11 22:04:39 +01:00
• f6ee25c5f9 Fix "TST" implementation Adrian Conlon 2026-05-11 21:59:13 +01:00
• e1470a13fa Simplify 6809 boolean flag handling Adrian Conlon 2026-05-11 19:18:11 +01:00
• f01762b9de Fix a small effective address problem Adrian Conlon 2026-05-11 17:30:38 +01:00
• f1c02dd012 Simplify long/short branch Adrian Conlon 2026-05-11 14:59:06 +01:00
• 0e48e86edf Correct LBSR implementation Adrian Conlon 2026-05-11 14:53:22 +01:00
• 1dfa94daf2 Small tidy ups Adrian Conlon 2026-05-11 14:37:54 +01:00
• ad97013127 Isolate effecitive address usage away from "intermediate" usage Adrian Conlon 2026-05-11 13:59:46 +01:00
• 71d7832e91 Sort out inherent addressing to be a little more consistent Adrian Conlon 2026-05-11 13:10:56 +01:00
• fa61bd4854 Update documentation links, including some wayback machinem for unavailable Adrian Conlon 2026-05-10 09:57:02 +01:00
• 5026c27582 Correct performance issue in "board" by fixing uncontrolled MemoryMapping allocations. Adrian Conlon 2026-05-09 18:23:13 +01:00
• da7f362754 Fix ASR implementation. Unify ANDCC / ORCC cycle waste Adrian Conlon 2026-05-09 17:31:05 +01:00
• 1c485bca22 Correct all obvious timing inaccuracies Adrian Conlon 2026-05-09 17:15:11 +01:00
• a9f2049c17 Current cycle checks/updates Adrian Conlon 2026-05-09 15:30:01 +01:00
• f093bf1e53 Work in progress Adrian Conlon 2026-05-09 14:11:07 +01:00
• b175086307 Mild overloading refactor for 6809 Adrian Conlon 2026-05-07 20:43:30 +01:00
• 224fe74e09 Refactor 6809 processor for readability Adrian Conlon 2026-05-07 17:11:42 +01:00
• 95b801b72f Correct a couple of anomolies in 6809 core Adrian Conlon 2026-05-05 21:29:10 +01:00
• d5b92b01c9 Tidy up everything I can see in 6809 implementation to bring it into line. Adrian Conlon 2026-05-05 19:19:13 +01:00
• 2bb004598e Simplify parity adjustment in block IO repeat code. Adrian Conlon 2026-05-03 11:37:02 +01:00
• 88d4ab5126 Fix final 4 opcodes for 100% harte singlestep test compatibility. hurrah! Adrian Conlon 2026-05-03 11:27:14 +01:00
• 69a0865ee9 Start work towards WDC 65C02 implementation Adrian Conlon 2026-05-02 17:02:36 +01:00
• 10106657d3 Some small cosmetic changes Adrian Conlon 2026-05-02 14:13:01 +01:00
• fa73a86121 Fix theoretical symbols parser issue Adrian Conlon 2026-05-02 13:47:44 +01:00
• cfc3169933 So there we have it. 100% Harte single step coverage/success for MOS 6502 Adrian Conlon 2026-05-02 13:47:04 +01:00
• de12029c13 Speedup Z80 by encouraging runtime inlining of code Adrian Conlon 2026-04-20 18:56:05 +01:00
• 699791f7a4 Simplify intermediate 16-bit register usage Adrian Conlon 2026-04-16 13:47:24 +01:00
• 53e33b9eef Some simplifications Adrian Conlon 2026-04-07 12:02:31 +01:00
• 284158247b Fix up 6502 test classes Adrian Conlon 2026-03-31 21:52:20 +01:00
• bb626b9e9e Simplify some memory update calls Adrian Conlon 2026-03-27 18:19:08 +00:00
• 47baff3740 Correct some 8080 timing mistakes Adrian Conlon 2026-03-27 18:16:09 +00:00
• c587da19c4 Interesting. At best agressive inlining had zero effect and may have slowed things down slightly Adrian Conlon 2026-03-27 18:15:02 +00:00
• 290f7583c5 Correct region mis-label Adrian Conlon 2026-03-27 18:14:24 +00:00
• 98448b0524 Small consistency changes for LR35902 core Adrian Conlon 2026-03-21 12:44:19 +00:00
• 45a57eea86 Coupld of small readability changes Adrian Conlon 2026-03-21 09:49:09 +00:00
• 0029427d6f Fix 8080 implementation to be closer to Z80 Adrian Conlon 2026-03-21 09:48:35 +00:00
• dcd98e5eb7 Simplify Z80 IM2 implementation Adrian Conlon 2026-03-20 09:55:40 +00:00
• a8ef9aa7db simplification and unification of build stuff Adrian Conlon 2026-02-16 11:15:58 +00:00
• e1bf58afbc More sharing of concepts between all Intel style processors Adrian Conlon 2026-01-03 23:17:30 +00:00
• 810d05a50e tidy the intel op-code decoder a little Adrian Conlon 2025-11-27 16:49:44 +00:00
• 1dfd9621a1 Share some more common code between Intel style procesors Adrian Conlon 2025-10-15 19:46:10 +01:00
• 33fce45cc8 Some performance updates Adrian Conlon 2025-10-13 17:36:32 +01:00
• ceacac4741 Fix up some oddities in the EightBit library Adrian Conlon 2025-10-06 13:44:31 +01:00
• 3ca62c908c Simplify Z80 pn-handling a little Adrian Conlon 2025-09-11 08:34:24 +01:00
• 2bd50e5cd2 Fix the single step checker a little Adrian Conlon 2025-08-25 23:57:52 +01:00
• 17a2b99d6c Remove all cycle accurate processing Adrian Conlon 2025-08-25 23:56:27 +01:00
• 1779d1dc40 Intel processors all seem to act slightly differently with regards to HALT Adrian Conlon 2025-08-17 12:03:51 +01:00
• c67e376d4f Add support for checking deferred EI correctness Adrian Conlon 2025-08-14 14:57:51 +01:00
• 4da07a8fa2 Correct interrupt flag checks in Gameboy checker Adrian Conlon 2025-08-14 11:18:02 +01:00
• a4e704fef4 I give up. This is probably more compatible with Intel derived processors Adrian Conlon 2025-08-13 19:03:25 +01:00
• 7951abde00 Add support for "Gameboy Doctor" log checker. Adrian Conlon 2025-08-13 14:01:14 +01:00
• eb23fbe44c Correction: the least significant bit is *not* zeroed by an IM 2 interrupt Adrian Conlon 2025-08-12 17:19:55 +01:00
• e96a51342a Remove unneeded "using" Adrian Conlon 2025-08-12 08:28:08 +01:00
• 25ca534186 The EI instructions is actually a deferred instruction Adrian Conlon 2025-08-10 21:47:15 +01:00
• d4775cb266 Correct assertion failure during refresh cycle Adrian Conlon 2025-08-10 12:52:48 +01:00
• 558da38f12 Note commonality between Intel-style processors Adrian Conlon 2025-08-10 12:43:34 +01:00
• 2e1573b016 Add support for sub-M-cycle accuracy. Not sure how useful this is! Adrian Conlon 2025-08-10 11:32:53 +01:00
• 072e38f6ee Add a couple of debug assertions Adrian Conlon 2025-08-09 15:10:27 +01:00
• b40224b5af Correct IM 2 indirection Adrian Conlon 2025-08-09 14:52:41 +01:00
• f1febd480e Sort out interrupt timing (I think) Adrian Conlon 2025-08-09 13:29:57 +01:00
• e8a1e7dc6e Sort out Z80/Spectrum pin handling (again!) Adrian Conlon 2025-08-08 21:47:48 +01:00
• 199d0a77b1 Disable interrups as the first act of INT handling Adrian Conlon 2025-08-08 00:03:21 +01:00
• 41be64ad99 Simplfy interrupts on Z80 Adrian Conlon 2025-08-07 19:05:41 +01:00
• d332c57e47 Simplify Z80 port handling Adrian Conlon 2025-08-07 09:56:25 +01:00
• 3a8e379efd Align with Z80 implementation Adrian Conlon 2025-08-07 09:42:52 +01:00
• ed6c7968bd Remove effectively impossible to use methods Adrian Conlon 2025-08-07 09:42:23 +01:00
• 14e4132d34 Small consistency change Adrian Conlon 2025-08-06 16:54:14 +01:00
• 350483fcec Catch another couple of Z80 timing issues Adrian Conlon 2025-08-05 00:14:05 +01:00
• 796042acdf Simplfy intel processor interations Adrian Conlon 2025-08-04 19:47:40 +01:00
• 52ea4b3acd Last trivial Z80 update Adrian Conlon 2025-08-04 18:19:40 +01:00
• 9d208de9bb Explicitly state order of operations in code, rather than relying upon RAII etc. (for speed. Much faster) Adrian Conlon 2025-08-04 15:47:26 +01:00
• 319190b7a5 More Z80 cycle simplifications and fixes Adrian Conlon 2025-08-03 21:55:24 +01:00
• 6a32d0269d Fix the Z80 checker, so that all cycle actions are checked. Adrian Conlon 2025-08-03 21:54:05 +01:00
• 3ccd9c45ca Adjusted for the latest single-step Z80 tests. Simplify memory update access. Adrian Conlon 2025-08-02 17:49:18 +01:00
• bfc2355337 Correct RRD/RLD timing and XHTL ordering (according to latest Z80 single step tests) Adrian Conlon 2025-08-02 12:26:53 +01:00
• 6143a9d285 Hack to allow single step tests to completely work: disable IO area triggers. Adrian Conlon 2025-08-01 22:59:00 +01:00
• bb63211f17 Fix event names Adrian Conlon 2025-08-01 22:57:38 +01:00
• 60ef099208 Tidy some inconsistencies in various emulation Adrian Conlon 2025-08-01 15:01:20 +01:00
• a252a74d2d Tidy some inconsistencies in z80 emulation Adrian Conlon 2025-08-01 14:59:40 +01:00
• 2f338c6c46 Tidy register increment/decrement a little. Adrian Conlon 2025-07-25 16:32:30 +01:00
• c271b28495 Simplify bus addressing Adrian Conlon 2025-07-05 09:46:59 +01:00
• 3bbf300e05 Simplify switching processor pin handling Adrian Conlon 2025-06-22 21:07:02 +01:00
• 3105930027 Fix BBR/BBS timings in 65C02 Adrian Conlon 2025-06-19 13:27:05 +01:00
• caca3467d9 More unit test stuff. New tests generated by copilot Adrian Conlon 2025-05-13 09:52:12 +01:00
• 12053fd076 Tidy 6809 tests namespace Adrian Conlon 2025-05-12 21:39:42 +01:00
• a5eed89b26 Tidy up all the 6809 stuff Adrian Conlon 2025-05-12 21:08:39 +01:00
• 6e1fc14530 Start tidying up 6809 implementation/testst Adrian Conlon 2025-05-12 19:15:34 +01:00
• adbd16daa2 Get M6809 unit tests running again Adrian Conlon 2025-05-12 12:19:27 +01:00
• e7b025e66e Some speed-up refactoring of the Z80 core Adrian Conlon 2025-05-12 10:17:39 +01:00
• 8331b4818e Couple of small Register16 adjustments Adrian Conlon 2025-05-11 21:30:15 +01:00