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Mikey enumeration values for cc65 include files and new bit definitions for ca65
This commit is contained in:
Alex Thissen
Alex Thissen
parent
394d3b1964
commit
eb6003aaf7
185
asminc/lynx.inc
185
asminc/lynx.inc
@ -138,8 +138,9 @@ HOWIE = $FCC4
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; *** Mikey Addresses
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; ***
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; Mikey Timers
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; Mikey timers
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; Logical timer names
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TIMER0 = $FD00
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TIMER1 = $FD04
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TIMER2 = $FD08
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@ -148,9 +149,9 @@ TIMER4 = $FD10
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TIMER5 = $FD14
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TIMER6 = $FD18
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TIMER7 = $FD1C
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HTIMER = $FD00 ; horizontal line timer (timer 0)
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VTIMER = $FD08 ; vertical blank timer (timer 2)
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STIMER = $FD1C ; sound timer (timer 7)
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HTIMER = TIMER0 ; horizontal line timer (timer 0)
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VTIMER = TIMER2 ; vertical blank timer (timer 2)
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STIMER = TIMER7 ; sound timer (timer 7)
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HTIMBKUP = $FD00 ; horizontal line timer (timer 0)
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HTIMCTLA = $FD01
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@ -199,6 +200,35 @@ TIM7CTLA = $FD1D
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TIM7CNT = $FD1E
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TIM7CTLB = $FD1F
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; Timer offsets
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TIM_BACKUP = 0
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TIM_CONTROLA = 1
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TIM_COUNT = 2
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TIM_CONTROLB = 3
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; TIM_CONTROLA control bits
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ENABLE_INT = %10000000
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RESET_DONE = %01000000
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ENABLE_RELOAD = %00010000
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ENABLE_COUNT = %00001000
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AUD_CLOCK_MASK = %00000111
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; Clock settings
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AUD_LINKING = %00000111
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AUD_64 = %00000110
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AUD_32 = %00000101
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AUD_16 = %00000100
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AUD_8 = %00000011
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AUD_4 = %00000010
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AUD_2 = %00000001
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AUD_1 = %00000000
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; TIM_CONTROLB control bits
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TIMER_DONE = %00001000
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LAST_CLOCK = %00000100
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BORROW_IN = %00000010
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BORROW_OUT = %00000001
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; Mikey Audio
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AUDIO0 = $FD20 ; audio channel 0
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@ -238,85 +268,155 @@ AUD3BKUP = $FD3C
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AUD3CTLA = $FD3D
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AUD3CNT = $FD3E
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AUD3CTLB = $FD3F
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; AUD_CONTROL bits are almost identical to TIM_CONTROLA bits.
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; See TIM_CONTROLA above for the other definitions
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FEEDBACK_7 = %10000000
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ENABLE_INTEGRATE = %00100000
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; Stereo control registers follow
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; Stereo capability does not exist in all Lynxes
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; Left and right may be reversed, and if so will be corrected in a later
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; release
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ATTENREG0 = $FD40 ; Stereo attenuation registers
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ATTENREG1 = $FD41
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ATTENREG2 = $FD42
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ATTENREG3 = $FD43
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LEFT_ATTENMASK = %11110000
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RIGHT_ATTENMASK = %00001111
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; Bit definitions for MPAN and MSTEREO registers
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LEFT3_SELECT = %10000000
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LEFT2_SELECT = %01000000
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LEFT1_SELECT = %00100000
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LEFT0_SELECT = %00010000
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RIGHT3_SELECT = %00001000
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RIGHT2_SELECT = %00000100
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RIGHT1_SELECT = %00000010
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RIGHT0_SELECT = %00000001
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MPAN = $FD44
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MSTEREO = $FD50
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; Mikey Misc
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; Mikey interrupts
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INTRST = $FD80
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INTSET = $FD81
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; Interrupt bits in INTRST and INTSET
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TIMER0_INTERRUPT = $01
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TIMER1_INTERRUPT = $02
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TIMER2_INTERRUPT = $04
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TIMER3_INTERRUPT = $08
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TIMER4_INTERRUPT = $10
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TIMER5_INTERRUPT = $20
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TIMER6_INTERRUPT = $40
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TIMER7_INTERRUPT = $80
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TIMER0_INTERRUPT = %00000001
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TIMER1_INTERRUPT = %00000010
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TIMER2_INTERRUPT = %00000100
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TIMER3_INTERRUPT = %00001000
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TIMER4_INTERRUPT = %00010000
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TIMER5_INTERRUPT = %00100000
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TIMER6_INTERRUPT = %01000000
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TIMER7_INTERRUPT = %10000000
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HBL_INTERRUPT = TIMER0_INTERRUPT
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VBL_INTERRUPT = TIMER2_INTERRUPT
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SERIAL_INTERRUPT = TIMER4_INTERRUPT
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SND_INTERRUPT = TIMER7_INTERRUPT
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INTRST = $FD80
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INTSET = $FD81
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MAGRDY0 = $FD84
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MAGRDY1 = $FD85
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AUDIN = $FD86
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SYSCTL1 = $FD87
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; SYSCTL1 bit definitions
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POWERON = %00000010
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CART_ADDR_STROBE = %00000001
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MIKEYHREV = $FD88
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MIKEYSREV = $FD89
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IODIR = $FD8A
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IODAT = $FD8B
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; IODIR and IODAT bit definitions
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AUDIN_BIT = $10 ; Note that there is also the address AUDIN
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READ_ENABLE = $10 ; Same bit for AUDIN_BIT
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RESTLESS = $08
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NOEXP = $04 ; If set, redeye is not connected
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CART_ADDR_DATA = $02
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CART_POWER_OFF = $02 ; Same bit for CART_ADDR_DATA
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EXTERNAL_POWER = $01
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AUDIN_BIT = %00010000 ; Note that there is also the address AUDIN
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READ_ENABLE = %00010000 ; Same bit for AUDIN_BIT
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RESTLESS = %00001000
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NOEXP = %00000100 ; If set, redeye is not connected
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CART_ADDR_DATA = %00000010
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CART_POWER_OFF = %00000010 ; Same bit for CART_ADDR_DATA
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EXTERNAL_POWER = %00000001
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SERCTL = $FD8C
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; SERCTL bit definitions for write operations
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TXINTEN = $80
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RXINTEN = $40
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PAREN = $10
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RESETERR = $08
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TXOPEN = $04
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TXBRK = $02
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PAREVEN = $01
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TXINTEN = %10000000
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RXINTEN = %01000000
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PAREN = %00010000
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RESETERR = %00001000
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TXOPEN = %00000100
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TXBRK = %00000010
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PAREVEN = %00000001
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; SERCTL bit definitions for read operations
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TXRDY = $80
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RXRDY = $40
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TXEMPTY = $20
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PARERR = $10
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OVERRUN = $08
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FRAMERR = $04
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RXBRK = $02
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PARBIT = $01
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TXRDY = %10000000
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RXRDY = %01000000
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TXEMPTY = %00100000
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PARERR = %00010000
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OVERRUN = %00001000
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FRAMERR = %00000100
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RXBRK = %00000010
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PARBIT = %00000001
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SERDAT = $FD8D
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SDONEACK = $FD90
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CPUSLEEP = $FD91
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DISPCTL = $FD92
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; DISPCTL bit definitions
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DISP_COLOR = %10000000 ; must be set to 1
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DISP_FOURBIT = %01000000 ; must be set to 1
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DISP_FLIP = %00100000
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DMA_ENABLE = %00010000 ; must be set to 1
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PBKUP = $FD93
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DISPADRL = $FD94
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DISPADRH = $FD95
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MTEST0 = $FD9C
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; MTEST0 bit definitions
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AT_CNT16 = %10000000
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AT_TEST = %01000000
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XCLKEN = %00100000
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UART_TURBO = %00010000
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ROM_SEL = %00001000
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ROM_TEST = %00000100
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M_TEST = %00000010
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CPU_TEST = %00000001
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MTEST1 = $FD9D
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; MTEST1 bit definitions
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P_CNT16 = %01000000
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REF_CNT16 = %00100000
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VID_TRIG = %00010000
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REF_TRIG = %00001000
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VID_DMA_DIS = %00000100
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REF_FAST = %00000010
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REF_DIS = %00000001
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MTEST2 = $FD9E
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; MTEST2 bit definitions
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V_STROBE = %00010000
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V_ZERO = %00001000
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H_120 = %00000100
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H_ZERO = %00000010
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V_BLANKEF = %00000001
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PALETTE = $FDA0 ; hardware rgb palette
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GCOLMAP = $FDA0 ; hardware rgb palette (green)
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RBCOLMAP = $FDB0 ; hardware rgb palette (red-blue)
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; ***
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; *** Misc Hardware + 6502 vectors
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; ***
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; Memory mapping control and 6502 vectors
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MAPCTL = $FFF9
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; MAPCTL bit definitions
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TURBO_DISABLE = %10000000
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VECTOR_SPACE = %00001000 ; 1 maps RAM into specified space
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ROM_SPACE = %00000100
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MIKEY_SPACE = %00000010
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SUZY_SPACE = %00000001
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VECTORS = $FFFB
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INTVECTL = $FFFE
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INTVECTH = $FFFF
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@ -324,4 +424,3 @@ RSTVECTL = $FFFC
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RSTVECTH = $FFFD
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NMIVECTL = $FFFA
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NMIVECTH = $FFFB
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165
include/_mikey.h
165
include/_mikey.h
@ -27,7 +27,7 @@
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#ifndef __MIKEY_H
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#define __MIKEY_H
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/* timer structure */
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/* Timer structure */
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typedef struct _mikey_timer {
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unsigned char reload;
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unsigned char control;
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@ -39,7 +39,7 @@ typedef struct _mikey_all_timers {
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struct _mikey_timer timer[8];
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} _mikey_all_timers;
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/* audio channel structure */
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/* Audio channel structure */
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typedef struct _mikey_audio {
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unsigned char volume;
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unsigned char feedback;
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@ -98,9 +98,168 @@ struct __mikey {
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unsigned char mtest2; // 0xFD9E
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unsigned char unused5; // 0xFD9F not used
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unsigned char palette[32]; // 0xFDA0 - 0xFDBF palette 32 bytes
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// 0xFDC0 - 0xFDFF not used
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unsigned char unused6[64]; // 0xFDC0 - 0xFDFF not used
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unsigned char bootrom[504]; // 0xFE00 - 0xFFD8 boot rom
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unsigned char reserved; // 0xFFD8 reserved for future hardware
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unsigned char mapctl; // 0xFFF9 map control register
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struct {
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unsigned char *nmi; // 0xFFFA NMI vector
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unsigned char *reset; // 0xFFFB reset vector
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unsigned char *irq; // 0xFFFC IRQ vector
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} vectors;
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};
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// TIM_CONTROLA control bit definitions
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enum {
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ENABLE_INT = 0x80,
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RESET_DONE = 0x40,
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ENABLE_RELOAD = 0x10,
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ENABLE_COUNT = 0x08
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};
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// AUD_CONTROL control bit definitions
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enum {
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FEEDBACK_7 = 0x80,
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ENABLE_INTEGRATE = 0x20
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};
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// Audio and timer clock settings for source period
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enum {
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AUD_LINKING = 0x07,
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AUD_64 = 0x06,
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AUD_32 = 0x05,
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AUD_16 = 0x04,
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AUD_8 = 0x03,
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AUD_4 = 0x02,
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AUD_2 = 0x01,
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AUD_1 = 0x00
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};
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// TIM_CONTROLB control bit definitions
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enum {
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TIMER_DONE = 0x08,
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LAST_CLOCK = 0x04,
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BORROW_IN = 0x02,
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BORROW_OUT = 0x01
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};
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// MPAN and MSTEREO registers bit definitions
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enum {
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LEFT3_SELECT = 0x80,
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LEFT2_SELECT = 0x40,
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LEFT1_SELECT = 0x20,
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LEFT0_SELECT = 0x10,
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RIGHT3_SELECT = 0x08,
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RIGHT2_SELECT = 0x04,
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RIGHT1_SELECT = 0x02,
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RIGHT0_SELECT = 0x01,
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LEFT_ATTENMASK = 0xF0,
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RIGHT_ATTENMASK = 0x0F
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};
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// Interrupt Reset and Set bit definitions
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enum {
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TIMER7_INT = 0x80,
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TIMER6_INT = 0x40,
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TIMER5_INT = 0x20,
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TIMER4_INT = 0x10,
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TIMER3_INT = 0x08,
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TIMER2_INT = 0x04,
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TIMER1_INT = 0x02,
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TIMER0_INT = 0x01,
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SERIAL_INT = TIMER4_INT,
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VERTICAL_INT = TIMER2_INT,
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HORIZONTAL_INT = TIMER0_INT
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};
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// SYSCTL1 bit definitions
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enum {
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POWERON = 0x02,
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CART_ADDR_STROBE = 0x01
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};
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// IODIR and IODAT bit definitions
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enum {
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AUDIN_BIT = 0x10, // different from AUDIN address
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READ_ENABLE = 0x10, // same bit for AUDIN_BIT
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RESTLESS = 0x08,
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NOEXP = 0x04, // if set, redeye is not connected
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CART_ADDR_DATA = 0x02, //
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CART_POWER_OFF = 0x02, // same bit for CART_ADDR_DATA
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EXTERNAL_POWER = 0x01
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};
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// SERCTL bit definitions for write operations
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enum {
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TXINTEN = 0x80,
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RXINTEN = 0x40,
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PAREN = 0x10,
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RESETERR = 0x08,
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TXOPEN = 0x04,
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TXBRK = 0x02,
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PAREVEN = 0x01
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};
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// SERCTL bit definitions for read operations
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enum {
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TXRDY = 0x80,
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RXRDY = 0x40,
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TXEMPTY = 0x20,
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PARERR = 0x10,
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OVERRUN = 0x08,
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FRAMERR = 0x04,
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RXBRK = 0x02,
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PARBIT = 0x01
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};
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// DISPCTL bit definitions
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enum {
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DISP_COLOR = 0x08, // must be set to 1
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DISP_FOURBIT = 0x04, // must be set to 1
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DISP_FLIP = 0x02, //
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DMA_ENABLE = 0x01 // must be set to 1
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};
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// MTEST0 bit definitions
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enum {
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AT_CNT16 = 0x80,
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AT_TEST = 0x40,
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XCLKEN = 0x20,
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UART_TURBO = 0x10,
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ROM_SEL = 0x08,
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ROM_TEST = 0x04,
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M_TEST = 0x02,
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CPU_TEST = 0x01
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};
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// MTEST1 bit definitions
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enum {
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P_CNT16 = 0x40,
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REF_CNT16 = 0x20,
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VID_TRIG = 0x10,
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REF_TRIG = 0x08,
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VID_DMA_DIS = 0x04,
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REF_FAST = 0x02,
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REF_DIS = 0x01
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};
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// MTEST2 bit definitions
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enum {
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V_STROBE = 0x10,
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V_ZERO = 0x08,
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H_120 = 0x04,
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H_ZERO = 0x02,
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V_BLANKEF = 0x01
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};
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// MAPCTL bit definitions
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enum {
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TURBO_DISABLE = 0x80,
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VECTOR_SPACE = 0x08,
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ROM_SPACE = 0x04,
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MIKEY_SPACE = 0x02,
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SUZY_SPACE = 0x01
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};
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#endif
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