2004-09-22 21:48:50 +00:00
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//===- SparcV8RegisterInfo.td - SparcV8 Register defs ------*- tablegen -*-===//
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2004-02-25 19:28:19 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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2004-09-22 21:48:50 +00:00
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//===----------------------------------------------------------------------===//
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2004-02-25 21:00:05 +00:00
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// Declarations that describe the SparcV8 register file
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2004-02-25 19:28:19 +00:00
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//===----------------------------------------------------------------------===//
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2004-09-22 21:48:50 +00:00
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class SparcReg<string n> : Register<n> {
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field bits<5> Num;
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let Namespace = "V8";
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2004-04-07 04:01:11 +00:00
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}
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2004-09-22 21:48:50 +00:00
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include "../SparcRegisterInfo.td"
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2004-02-25 19:28:19 +00:00
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2004-03-04 05:15:03 +00:00
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// Register classes.
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2004-02-25 21:00:05 +00:00
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//
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// FIXME: the register order should be defined in terms of the preferred
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// allocation order...
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//
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2004-09-27 18:22:18 +00:00
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def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
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2004-03-08 03:48:07 +00:00
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I0, I1, I2, I3, I4, I5,
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2004-11-18 00:25:20 +00:00
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G1,
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2004-06-18 08:19:08 +00:00
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O0, O1, O2, O3, O4, O5, O7,
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2004-11-18 00:25:20 +00:00
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// Non-allocatable regs:
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G2, G3, G4, // FIXME: OK for use only in
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// applications, not libraries.
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O6, // stack ptr
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I6, // frame ptr
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I7, // return address
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G0, // constant zero
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G5, G6, G7 // reserved for kernel
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]> {
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2004-03-08 03:48:07 +00:00
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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2004-11-18 00:25:20 +00:00
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return end()-10; // Don't allocate special registers
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2004-03-08 03:48:07 +00:00
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}
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}];
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}
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2004-03-04 04:37:22 +00:00
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2004-08-21 20:09:46 +00:00
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def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
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2004-03-04 04:37:22 +00:00
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F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
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F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
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2004-03-04 05:15:03 +00:00
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2004-08-21 20:09:46 +00:00
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def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
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2004-03-04 05:15:03 +00:00
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D8, D9, D10, D11, D12, D13, D14, D15]>;
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