2013-08-13 20:19:16 +00:00
|
|
|
def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
|
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|
|
def simm12 : Operand<i32> {
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let DecoderMethod = "DecodeSimm12";
|
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|
|
}
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|
def mem_mm_12 : Operand<i32> {
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|
let PrintMethod = "printMemOperand";
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|
let MIOperandInfo = (ops GPR32, simm12);
|
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|
let EncoderMethod = "getMemEncodingMMImm12";
|
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let ParserMatchClass = MipsMemAsmOperand;
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let OperandType = "OPERAND_MEMORY";
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}
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|
2013-10-29 16:38:59 +00:00
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|
def jmptarget_mm : Operand<OtherVT> {
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|
let EncoderMethod = "getJumpTargetOpValueMM";
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}
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def calltarget_mm : Operand<iPTR> {
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let EncoderMethod = "getJumpTargetOpValueMM";
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}
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2013-11-04 14:53:22 +00:00
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def brtarget_mm : Operand<OtherVT> {
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let EncoderMethod = "getBranchTargetOpValueMM";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTargetMM";
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}
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2013-08-13 20:19:16 +00:00
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|
let canFoldAsLoad = 1 in
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class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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Operand MemOpnd> :
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InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
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!strconcat(opstr, "\t$rt, $addr"),
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[(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
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NoItinerary, FrmI> {
|
2013-09-06 12:30:36 +00:00
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|
let DecoderMethod = "DecodeMemMMImm12";
|
2013-08-13 20:19:16 +00:00
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|
string Constraints = "$src = $rt";
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|
}
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class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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|
Operand MemOpnd>:
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|
InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
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|
|
|
!strconcat(opstr, "\t$rt, $addr"),
|
2013-09-06 12:30:36 +00:00
|
|
|
[(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
|
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|
|
|
let DecoderMethod = "DecodeMemMMImm12";
|
|
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|
|
}
|
2013-08-13 20:19:16 +00:00
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|
2013-12-19 16:12:56 +00:00
|
|
|
class LLBaseMM<string opstr, RegisterOperand RO> :
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|
InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
|
|
|
|
|
!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
|
2014-01-15 13:17:33 +00:00
|
|
|
let DecoderMethod = "DecodeMemMMImm12";
|
2013-12-19 16:12:56 +00:00
|
|
|
let mayLoad = 1;
|
|
|
|
|
}
|
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|
|
class SCBaseMM<string opstr, RegisterOperand RO> :
|
2014-02-28 18:22:56 +00:00
|
|
|
InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
|
2013-12-19 16:12:56 +00:00
|
|
|
!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
|
2014-01-15 13:17:33 +00:00
|
|
|
let DecoderMethod = "DecodeMemMMImm12";
|
2013-12-19 16:12:56 +00:00
|
|
|
let mayStore = 1;
|
2014-02-28 18:22:56 +00:00
|
|
|
let Constraints = "$rt = $dst";
|
2013-12-19 16:12:56 +00:00
|
|
|
}
|
|
|
|
|
|
2014-01-15 13:01:18 +00:00
|
|
|
class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
|
|
|
|
|
InstrItinClass Itin = NoItinerary> :
|
|
|
|
|
InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
|
|
|
|
|
!strconcat(opstr, "\t$rt, $addr"),
|
|
|
|
|
[(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
|
|
|
|
|
let DecoderMethod = "DecodeMemMMImm12";
|
|
|
|
|
let canFoldAsLoad = 1;
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-20 20:46:51 +00:00
|
|
|
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
|
2013-04-19 19:03:11 +00:00
|
|
|
/// Arithmetic Instructions (ALU Immediate)
|
2013-08-06 23:08:38 +00:00
|
|
|
def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
|
2013-04-19 19:03:11 +00:00
|
|
|
ADDI_FM_MM<0xc>;
|
2013-08-06 23:08:38 +00:00
|
|
|
def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
|
2013-04-19 19:03:11 +00:00
|
|
|
ADDI_FM_MM<0x4>;
|
2013-08-06 23:08:38 +00:00
|
|
|
def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
|
2013-04-19 19:03:11 +00:00
|
|
|
SLTI_FM_MM<0x24>;
|
2013-08-06 23:08:38 +00:00
|
|
|
def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
|
2013-04-19 19:03:11 +00:00
|
|
|
SLTI_FM_MM<0x2c>;
|
2013-08-06 23:08:38 +00:00
|
|
|
def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
|
2013-04-19 19:03:11 +00:00
|
|
|
ADDI_FM_MM<0x34>;
|
2013-08-06 23:08:38 +00:00
|
|
|
def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
|
2013-04-19 19:03:11 +00:00
|
|
|
ADDI_FM_MM<0x14>;
|
2013-08-06 23:08:38 +00:00
|
|
|
def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
|
2013-04-19 19:03:11 +00:00
|
|
|
ADDI_FM_MM<0x1c>;
|
2013-08-06 23:08:38 +00:00
|
|
|
def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
|
2013-04-19 19:03:11 +00:00
|
|
|
|
2013-12-25 10:14:07 +00:00
|
|
|
def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
|
|
|
|
|
LW_FM_MM<0xc>;
|
|
|
|
|
|
2013-04-19 19:03:11 +00:00
|
|
|
/// Arithmetic Instructions (3-Operand, R-Type)
|
2013-08-06 23:08:38 +00:00
|
|
|
def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
|
|
|
|
|
def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
|
|
|
|
|
def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
|
|
|
|
|
def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
|
|
|
|
|
def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
|
|
|
|
|
def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
|
|
|
|
|
def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
|
2013-04-19 19:03:11 +00:00
|
|
|
ADD_FM_MM<0, 0x390>;
|
2014-01-16 17:13:57 +00:00
|
|
|
def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
|
2013-04-19 19:03:11 +00:00
|
|
|
ADD_FM_MM<0, 0x250>;
|
2014-01-16 17:13:57 +00:00
|
|
|
def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
|
2013-04-19 19:03:11 +00:00
|
|
|
ADD_FM_MM<0, 0x290>;
|
2014-01-16 17:13:57 +00:00
|
|
|
def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
|
2013-04-19 19:03:11 +00:00
|
|
|
ADD_FM_MM<0, 0x310>;
|
2013-08-06 23:08:38 +00:00
|
|
|
def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
|
2014-01-17 14:32:41 +00:00
|
|
|
def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
|
2013-04-19 19:03:11 +00:00
|
|
|
MULT_FM_MM<0x22c>;
|
2014-01-17 14:32:41 +00:00
|
|
|
def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
|
2013-04-19 19:03:11 +00:00
|
|
|
MULT_FM_MM<0x26c>;
|
2014-01-17 14:48:06 +00:00
|
|
|
def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
|
2013-09-14 07:15:21 +00:00
|
|
|
MULT_FM_MM<0x2ac>;
|
2014-01-17 14:48:06 +00:00
|
|
|
def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
|
2013-09-14 07:15:21 +00:00
|
|
|
MULT_FM_MM<0x2ec>;
|
2013-04-25 01:11:15 +00:00
|
|
|
|
|
|
|
|
/// Shift Instructions
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
|
2013-04-25 01:11:15 +00:00
|
|
|
SRA_FM_MM<0, 0>;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
|
2013-04-25 01:11:15 +00:00
|
|
|
SRA_FM_MM<0x40, 0>;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
|
2013-04-25 01:11:15 +00:00
|
|
|
SRA_FM_MM<0x80, 0>;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
|
2013-04-25 01:11:15 +00:00
|
|
|
SRLV_FM_MM<0x10, 0>;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
|
2013-04-25 01:11:15 +00:00
|
|
|
SRLV_FM_MM<0x50, 0>;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
|
2013-04-25 01:11:15 +00:00
|
|
|
SRLV_FM_MM<0x90, 0>;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
|
|
|
def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
|
2013-04-25 01:11:15 +00:00
|
|
|
SRA_FM_MM<0xc0, 0>;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
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def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
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2013-04-25 01:11:15 +00:00
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SRLV_FM_MM<0xd0, 0>;
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2013-04-25 01:21:25 +00:00
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/// Load and Store Instructions - aligned
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2013-09-06 12:30:36 +00:00
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let DecoderMethod = "DecodeMemMMImm16" in {
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def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
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def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
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def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
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def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
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def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
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def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
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def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
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def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
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}
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2013-08-13 20:19:16 +00:00
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2014-01-21 15:21:14 +00:00
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def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
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2014-01-15 13:01:18 +00:00
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2013-08-13 20:19:16 +00:00
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/// Load and Store Instructions - unaligned
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2013-08-20 20:46:51 +00:00
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def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x0>;
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def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x1>;
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def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x8>;
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def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x9>;
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2013-09-06 12:41:17 +00:00
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/// Move Conditional
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def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
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NoItinerary>, ADD_FM_MM<0, 0x58>;
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def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
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NoItinerary>, ADD_FM_MM<0, 0x18>;
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2014-01-16 17:13:57 +00:00
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def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
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2013-09-06 12:41:17 +00:00
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CMov_F_I_FM_MM<0x25>;
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2014-01-16 17:13:57 +00:00
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def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
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2013-09-06 12:41:17 +00:00
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CMov_F_I_FM_MM<0x5>;
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2013-09-06 12:53:21 +00:00
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/// Move to/from HI/LO
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def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
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MTLO_FM_MM<0x0b5>;
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def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
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MTLO_FM_MM<0x0f5>;
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2013-10-07 18:49:46 +00:00
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def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
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2013-09-06 12:53:21 +00:00
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MFLO_FM_MM<0x035>;
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2013-10-07 18:49:46 +00:00
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def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
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2013-09-06 12:53:21 +00:00
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MFLO_FM_MM<0x075>;
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2013-09-06 13:08:00 +00:00
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/// Multiply Add/Sub Instructions
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2014-01-17 14:32:41 +00:00
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def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
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def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
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def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
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def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
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2013-09-14 06:49:25 +00:00
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/// Count Leading
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def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>;
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def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>;
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/// Sign Ext In Register Instructions.
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2014-01-16 16:19:38 +00:00
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def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM_MM<0x0ac>;
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def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM_MM<0x0ec>;
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2013-09-14 06:49:25 +00:00
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/// Word Swap Bytes Within Halfwords
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def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>;
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def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
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EXT_FM_MM<0x2c>;
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def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
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EXT_FM_MM<0x0c>;
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2013-10-29 16:38:59 +00:00
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/// Jump Instructions
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let DecoderMethod = "DecodeJumpTargetMM" in {
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def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
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J_FM_MM<0x35>;
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def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
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}
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def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
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def JALR_MM : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
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def RET_MM : MMRel, RetBase<"ret", GPR32Opnd>, JR_FM_MM<0x3c>;
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2013-11-04 14:53:22 +00:00
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/// Branch Instructions
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def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
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BEQ_FM_MM<0x25>;
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def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
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BEQ_FM_MM<0x2d>;
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def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
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BGEZ_FM_MM<0x2>;
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def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
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BGEZ_FM_MM<0x6>;
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def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
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BGEZ_FM_MM<0x4>;
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def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
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BGEZ_FM_MM<0x0>;
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def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
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BGEZAL_FM_MM<0x03>;
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def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
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BGEZAL_FM_MM<0x01>;
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2013-11-07 14:35:24 +00:00
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2013-12-19 16:25:00 +00:00
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/// Control Instructions
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def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
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def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
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def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
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def WAIT_MM : MMRel, WAIT_FT<"wait">, WAIT_FM_MM;
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def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
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def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
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def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>;
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def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>;
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2013-11-07 14:35:24 +00:00
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/// Trap Instructions
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def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
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def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
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def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
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def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
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def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
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def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
|
2013-11-13 13:15:03 +00:00
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def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
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def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
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def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
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def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
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def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
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def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
|
2013-12-19 16:12:56 +00:00
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/// Load-linked, Store-conditional
|
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|
def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
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|
def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
|
2013-04-19 19:03:11 +00:00
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}
|
