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llvm-6502/test/CodeGen/ARM/inlineasm3.ll

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Add support for the 'j' immediate constraint. This is conditionalized on supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 01:00:07 +00:00
; RUN: llc < %s -march=arm -mattr=+neon,+v6t2 | FileCheck %s
- Support inline asm 'w' constraint for 128-bit vector types. - Also support the 'q' NEON registers asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-08 23:06:22 +00:00
Handle ARM inline asm "w" constraints with 64-bit ("d") registers. The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 01:03:29 +00:00
; Radar 7449043
- Support inline asm 'w' constraint for 128-bit vector types. - Also support the 'q' NEON registers asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-08 23:06:22 +00:00
%struct.int32x4_t = type { <4 x i32> }
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 15:18:27 +00:00
define void @t() nounwind {
- Support inline asm 'w' constraint for 128-bit vector types. - Also support the 'q' NEON registers asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-08 23:06:22 +00:00
entry:
; CHECK: vmov.I64 q15, #0
Make tests register allocation independent again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19 00:14:43 +00:00
; CHECK: vmov.32 d30[0],
Change register allocation order for ARM VFP and NEON registers to put the callee-saved registers at the end of the lists. Also prefer to avoid using the low registers that are in register subclasses required by certain instructions, so that those registers will more likely be available when needed. This change makes a huge improvement in spilling in some cases. Thanks to Jakob for helping me realize the problem. Most of this patch is fixing the testsuite. There are quite a few places where we're checking for specific registers. I changed those to wildcards in places where that doesn't weaken the tests. The spill-q.ll and thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch of live values to force spills on those tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 06:15:13 +00:00
; CHECK: vmov q8, q15
- Support inline asm 'w' constraint for 128-bit vector types. - Also support the 'q' NEON registers asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-08 23:06:22 +00:00
%tmp = alloca %struct.int32x4_t, align 16
call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind
ret void
}
Handle ARM inline asm "w" constraints with 64-bit ("d") registers. The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 01:03:29 +00:00
; Radar 7457110
%struct.int32x2_t = type { <4 x i32> }
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 15:18:27 +00:00
define void @t2() nounwind {
Handle ARM inline asm "w" constraints with 64-bit ("d") registers. The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 01:03:29 +00:00
entry:
Change register allocation order for ARM VFP and NEON registers to put the callee-saved registers at the end of the lists. Also prefer to avoid using the low registers that are in register subclasses required by certain instructions, so that those registers will more likely be available when needed. This change makes a huge improvement in spilling in some cases. Thanks to Jakob for helping me realize the problem. Most of this patch is fixing the testsuite. There are quite a few places where we're checking for specific registers. I changed those to wildcards in places where that doesn't weaken the tests. The spill-q.ll and thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch of live values to force spills on those tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 06:15:13 +00:00
; CHECK: vmov d30, d16
Handle ARM inline asm "w" constraints with 64-bit ("d") registers. The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 01:03:29 +00:00
; CHECK: vmov.32 r0, d30[0]
%asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind
ret void
}
Allow bitcasts between valid types of the same size and vector types if the vector type is legal. Fixes rdar://9306086 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 19:55:10 +00:00
; Radar 9306086
%0 = type { <8 x i8>, <16 x i8>* }
define hidden void @conv4_8_E() nounwind {
entry:
Make ARMAsmParser accept the correct alignment specifier syntax in instructions. The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 14:46:12 +00:00
%asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1:128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind
Allow bitcasts between valid types of the same size and vector types if the vector type is legal. Fixes rdar://9306086 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 19:55:10 +00:00
unreachable
}
Make the Uv constraint a memory operand. This doesn't solve the addressing mode problem mentioned in r132559. Backend part of rdar://9037836 and part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03 17:24:37 +00:00
; Radar 9037836 & 9119939
define i32 @t3() nounwind {
entry:
tail call void asm sideeffect "flds s15, $0 \0A", "^Uv|m,~{s15}"(float 1.000000e+00) nounwind
ret i32 0
}
Fix an off by one error. Part of rdar://9037836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03 20:44:52 +00:00
; Radar 9037836 & 9119939
@k.2126 = internal unnamed_addr global float 1.000000e+00
define i32 @t4() nounwind {
entry:
call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(float* @k.2126) nounwind
ret i32 0
}
Another possible bug. Stopgap until we can autogenerate tables and constraint lengths. Part of rdar://9037836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132598 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03 22:09:12 +00:00
; Radar 9037836 & 9119939
define i32 @t5() nounwind {
entry:
call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind
ret i32 0
}
Add support for the 'x' constraint. Part of rdar://9307836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 00:14:47 +00:00
; Radar 9307836 & 9119939
define float @t6(float %y) nounwind {
entry:
; CHECK: t6
; CHECK: flds s15, s0
%0 = tail call float asm "flds s15, $0", "=x"() nounwind
ret float %0
}
Add support for the ARM 't' register constraint. And another testcase for the 'x' register constraint. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 00:30:46 +00:00
; Radar 9307836 & 9119939
Add support for the 'j' immediate constraint. This is conditionalized on supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 01:00:07 +00:00
define double @t7(double %y) nounwind {
Add support for the ARM 't' register constraint. And another testcase for the 'x' register constraint. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 00:30:46 +00:00
entry:
; CHECK: t7
; CHECK: flds s15, d0
%0 = tail call double asm "flds s15, $0", "=x"() nounwind
ret double %0
}
; Radar 9307836 & 9119939
Add support for the 'j' immediate constraint. This is conditionalized on supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 01:00:07 +00:00
define float @t8(float %y) nounwind {
Add support for the ARM 't' register constraint. And another testcase for the 'x' register constraint. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 00:30:46 +00:00
entry:
; CHECK: t8
; CHECK: flds s15, s0
%0 = tail call float asm "flds s15, $0", "=t"() nounwind
ret float %0
}
Add support for the 'j' immediate constraint. This is conditionalized on supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 01:00:07 +00:00
; Radar 9307836 & 9119939
define i32 @t9(i32 %r0) nounwind {
entry:
; CHECK: t9
; CHECK: movw r0, #27182
%0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind
ret i32 %0
}
Add support for the 'Q' constraint. Fixes rdar://9866494 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136523 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 21:18:58 +00:00
; Radar 9866494
define void @t10(i8* %f, i32 %g) nounwind {
entry:
; CHECK: t10
; CHECK: str r1, [r0]
%f.addr = alloca i8*, align 4
store i8* %f, i8** %f.addr, align 4
call void asm "str $1, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind
ret void
}
Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006> These modifiers simply select either the low or high D subregister of a Neon Q register. I've also removed the unimplemented 'p' modifier, which turns out to be a bit different than the comment here suggests and as far as I can tell was only intended for internal use in Apple's version of gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146417 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 21:45:15 +00:00
; Radar 10551006
define <4 x i32> @t11(i32* %p) nounwind {
entry:
; CHECK: t11
; CHECK: vld1.s32 {d16[], d17[]}, [r0]
%0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(i32* %p) nounwind
ret <4 x i32> %0
}
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