2006-01-21 02:32:06 +00:00
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//===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
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2005-08-18 18:45:24 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2005-10-31 12:49:09 +00:00
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// This file was developed by James M. Laskey and is distributed under the
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2005-08-18 18:45:24 +00:00
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2005-09-26 21:57:04 +00:00
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// This implements a simple two pass scheduler. The first pass attempts to push
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// backward any lengthy instructions and critical paths. The second pass packs
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// instructions into semi-optimal time slots.
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2005-08-18 18:45:24 +00:00
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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2005-08-26 17:15:30 +00:00
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#include "llvm/CodeGen/MachineConstantPool.h"
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2005-08-19 20:45:43 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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2006-01-21 02:32:06 +00:00
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#include "llvm/CodeGen/ScheduleDAG.h"
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2005-08-19 20:45:43 +00:00
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#include "llvm/CodeGen/SSARegMap.h"
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2005-08-18 20:07:59 +00:00
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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2005-11-04 04:05:35 +00:00
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#include "llvm/Target/TargetInstrItineraries.h"
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2005-08-26 20:54:47 +00:00
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#include "llvm/Target/TargetLowering.h"
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2005-09-26 21:57:04 +00:00
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#include "llvm/Support/Debug.h"
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#include <iostream>
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2005-08-18 18:45:24 +00:00
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using namespace llvm;
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2005-09-26 21:57:04 +00:00
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands (which do
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/// not go into the machine instrs.)
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2006-01-21 02:32:06 +00:00
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static unsigned CountResults(SDNode *Node) {
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2005-09-30 19:15:27 +00:00
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unsigned N = Node->getNumValues();
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while (N && Node->getValueType(N - 1) == MVT::Flag)
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2005-09-26 21:57:04 +00:00
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--N;
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2005-09-30 19:15:27 +00:00
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if (N && Node->getValueType(N - 1) == MVT::Other)
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2005-09-26 21:57:04 +00:00
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--N; // Skip over chain result.
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return N;
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}
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/// CountOperands The inputs to target nodes have any actual inputs first,
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/// followed by an optional chain operand, then flag operands. Compute the
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/// number of actual operands that will go into the machine instr.
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2006-01-21 02:32:06 +00:00
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static unsigned CountOperands(SDNode *Node) {
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2005-09-30 19:15:27 +00:00
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unsigned N = Node->getNumOperands();
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while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
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2005-09-26 21:57:04 +00:00
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--N;
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2005-09-30 19:15:27 +00:00
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if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
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2005-09-26 21:57:04 +00:00
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--N; // Ignore chain if it exists.
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return N;
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}
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2006-01-23 07:01:07 +00:00
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/// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
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///
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void ScheduleDAG::PrepareNodeInfo() {
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// Allocate node information
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Info = new NodeInfo[NodeCount];
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unsigned i = 0;
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for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
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E = DAG.allnodes_end(); I != E; ++I, ++i) {
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// Fast reference to node schedule info
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NodeInfo* NI = &Info[i];
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// Set up map
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Map[I] = NI;
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// Set node
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NI->Node = I;
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// Set pending visit count
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NI->setPending(I->use_size());
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}
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}
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/// IdentifyGroups - Put flagged nodes into groups.
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///
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void ScheduleDAG::IdentifyGroups() {
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for (unsigned i = 0, N = NodeCount; i < N; i++) {
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NodeInfo* NI = &Info[i];
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SDNode *Node = NI->Node;
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// For each operand (in reverse to only look at flags)
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for (unsigned N = Node->getNumOperands(); 0 < N--;) {
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// Get operand
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SDOperand Op = Node->getOperand(N);
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// No more flags to walk
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if (Op.getValueType() != MVT::Flag) break;
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// Add to node group
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NodeGroup::Add(getNI(Op.Val), NI);
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2006-01-25 09:13:41 +00:00
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// Let everyone else know
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2006-01-23 07:01:07 +00:00
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HasGroups = true;
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}
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}
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}
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static unsigned CreateVirtualRegisters(MachineInstr *MI,
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unsigned NumResults,
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SSARegMap *RegMap,
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const TargetInstrDescriptor &II) {
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2005-09-26 21:57:04 +00:00
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// Create the result registers for this node and add the result regs to
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// the machine instruction.
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const TargetOperandInfo *OpInfo = II.OpInfo;
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unsigned ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
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MI->addRegOperand(ResultReg, MachineOperand::Def);
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for (unsigned i = 1; i != NumResults; ++i) {
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assert(OpInfo[i].RegClass && "Isn't a register operand!");
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2005-10-01 07:45:09 +00:00
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MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass),
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2005-09-26 21:57:04 +00:00
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MachineOperand::Def);
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}
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return ResultReg;
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}
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2005-09-30 19:15:27 +00:00
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/// EmitNode - Generate machine code for an node and needed dependencies.
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///
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2006-01-21 02:32:06 +00:00
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void ScheduleDAG::EmitNode(NodeInfo *NI) {
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2005-09-30 19:15:27 +00:00
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unsigned VRBase = 0; // First virtual register for node
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SDNode *Node = NI->Node;
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// If machine instruction
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if (Node->isTargetOpcode()) {
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unsigned Opc = Node->getTargetOpcode();
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2006-01-21 02:32:06 +00:00
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const TargetInstrDescriptor &II = TII->get(Opc);
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2005-09-30 19:15:27 +00:00
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unsigned NumResults = CountResults(Node);
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unsigned NodeOperands = CountOperands(Node);
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unsigned NumMIOperands = NodeOperands + NumResults;
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#ifndef NDEBUG
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assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&&
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"#operands for dag node doesn't match .td file!");
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#endif
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// Create the new machine instruction.
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MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true);
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// Add result register values for things that are defined by this
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// instruction.
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2005-10-30 18:54:27 +00:00
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// If the node is only used by a CopyToReg and the dest reg is a vreg, use
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// the CopyToReg'd destination register instead of creating a new vreg.
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if (NumResults == 1) {
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *Use = *UI;
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if (Use->getOpcode() == ISD::CopyToReg &&
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Use->getOperand(2).Val == Node) {
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unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(Reg)) {
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VRBase = Reg;
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MI->addRegOperand(Reg, MachineOperand::Def);
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break;
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}
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}
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}
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}
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// Otherwise, create new virtual registers.
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if (NumResults && VRBase == 0)
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2006-01-23 07:01:07 +00:00
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VRBase = CreateVirtualRegisters(MI, NumResults, RegMap, II);
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2005-09-30 19:15:27 +00:00
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// Emit all of the actual operands of this instruction, adding them to the
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// instruction as appropriate.
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for (unsigned i = 0; i != NodeOperands; ++i) {
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if (Node->getOperand(i).isTargetOpcode()) {
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// Note that this case is redundant with the final else block, but we
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// include it because it is the most common and it makes the logic
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// simpler here.
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assert(Node->getOperand(i).getValueType() != MVT::Other &&
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Node->getOperand(i).getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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2005-10-01 07:45:09 +00:00
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// Get/emit the operand.
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unsigned VReg = getVR(Node->getOperand(i));
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MI->addRegOperand(VReg, MachineOperand::Use);
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2005-09-30 19:15:27 +00:00
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2005-10-01 07:45:09 +00:00
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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assert(II.OpInfo[i+NumResults].RegClass &&
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"Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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2005-09-30 19:15:27 +00:00
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} else if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
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MI->addZeroExtImm64Operand(C->getValue());
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} else if (RegisterSDNode*R =
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dyn_cast<RegisterSDNode>(Node->getOperand(i))) {
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MI->addRegOperand(R->getReg(), MachineOperand::Use);
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} else if (GlobalAddressSDNode *TGA =
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dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
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2005-11-30 02:04:11 +00:00
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MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
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2005-09-30 19:15:27 +00:00
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} else if (BasicBlockSDNode *BB =
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dyn_cast<BasicBlockSDNode>(Node->getOperand(i))) {
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MI->addMachineBasicBlockOperand(BB->getBasicBlock());
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} else if (FrameIndexSDNode *FI =
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dyn_cast<FrameIndexSDNode>(Node->getOperand(i))) {
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MI->addFrameIndexOperand(FI->getIndex());
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} else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(Node->getOperand(i))) {
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unsigned Idx = ConstPool->getConstantPoolIndex(CP->get());
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MI->addConstantPoolIndexOperand(Idx);
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} else if (ExternalSymbolSDNode *ES =
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dyn_cast<ExternalSymbolSDNode>(Node->getOperand(i))) {
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MI->addExternalSymbolOperand(ES->getSymbol(), false);
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} else {
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assert(Node->getOperand(i).getValueType() != MVT::Other &&
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Node->getOperand(i).getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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2005-10-01 07:45:09 +00:00
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unsigned VReg = getVR(Node->getOperand(i));
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MI->addRegOperand(VReg, MachineOperand::Use);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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assert(II.OpInfo[i+NumResults].RegClass &&
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"Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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2005-09-30 19:15:27 +00:00
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}
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}
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// Now that we have emitted all operands, emit this instruction itself.
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if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
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BB->insert(BB->end(), MI);
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} else {
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// Insert this instruction into the end of the basic block, potentially
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// taking some custom action.
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BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
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}
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} else {
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switch (Node->getOpcode()) {
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default:
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Node->dump();
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assert(0 && "This target-independent node should have been selected!");
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case ISD::EntryToken: // fall thru
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case ISD::TokenFactor:
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break;
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case ISD::CopyToReg: {
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2005-10-30 18:54:27 +00:00
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unsigned InReg = getVR(Node->getOperand(2));
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unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
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if (InReg != DestReg) // Coallesced away the copy?
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2006-01-21 02:32:06 +00:00
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MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
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RegMap->getRegClass(InReg));
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2005-09-30 19:15:27 +00:00
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break;
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}
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case ISD::CopyFromReg: {
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unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(SrcReg)) {
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2005-10-09 05:58:56 +00:00
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VRBase = SrcReg; // Just use the input register directly!
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break;
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2005-09-30 19:15:27 +00:00
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}
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2005-10-09 05:58:56 +00:00
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2005-10-30 18:54:27 +00:00
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// If the node is only used by a CopyToReg and the dest reg is a vreg, use
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// the CopyToReg'd destination register instead of creating a new vreg.
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *Use = *UI;
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if (Use->getOpcode() == ISD::CopyToReg &&
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Use->getOperand(2).Val == Node) {
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unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(DestReg)) {
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VRBase = DestReg;
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break;
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}
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}
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}
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2005-10-09 05:58:56 +00:00
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// Figure out the register class to create for the destreg.
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const TargetRegisterClass *TRC = 0;
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2005-10-30 18:54:27 +00:00
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if (VRBase) {
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TRC = RegMap->getRegClass(VRBase);
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} else {
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2005-10-09 05:58:56 +00:00
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2005-10-30 18:54:27 +00:00
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// Pick the register class of the right type that contains this physreg.
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2006-01-21 02:32:06 +00:00
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for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
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E = MRI->regclass_end(); I != E; ++I)
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2005-12-01 04:51:06 +00:00
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if ((*I)->hasType(Node->getValueType(0)) &&
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2005-10-30 18:54:27 +00:00
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(*I)->contains(SrcReg)) {
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TRC = *I;
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break;
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}
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assert(TRC && "Couldn't find register class for reg copy!");
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2005-09-30 19:15:27 +00:00
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2005-10-30 18:54:27 +00:00
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// Create the reg, emit the copy.
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VRBase = RegMap->createVirtualRegister(TRC);
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}
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2006-01-21 02:32:06 +00:00
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MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
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2005-09-30 19:15:27 +00:00
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break;
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}
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2006-01-26 23:28:04 +00:00
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case ISD::INLINEASM: {
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unsigned NumOps = Node->getNumOperands();
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if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
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--NumOps; // Ignore the flag operand.
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// Create the inline asm machine instruction.
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MachineInstr *MI =
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new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
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// Add the asm string as an external symbol operand.
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const char *AsmStr =
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cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
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MI->addExternalSymbolOperand(AsmStr, false);
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// Add all of the operand registers to the instruction.
|
|
|
|
for (unsigned i = 2; i != NumOps; i += 2) {
|
|
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
unsigned Flags =cast<ConstantSDNode>(Node->getOperand(i+1))->getValue();
|
2006-01-26 23:28:04 +00:00
|
|
|
MachineOperand::UseType UseTy;
|
|
|
|
switch (Flags) {
|
|
|
|
default: assert(0 && "Bad flags!");
|
|
|
|
case 1: UseTy = MachineOperand::Use; break;
|
|
|
|
case 2: UseTy = MachineOperand::Def; break;
|
|
|
|
case 3: UseTy = MachineOperand::UseAndDef; break;
|
|
|
|
}
|
|
|
|
MI->addMachineRegOperand(Reg, UseTy);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2005-09-30 19:15:27 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(NI->VRBase == 0 && "Node emitted out of order - early");
|
|
|
|
NI->VRBase = VRBase;
|
|
|
|
}
|
|
|
|
|
2006-01-23 07:01:07 +00:00
|
|
|
/// EmitAll - Emit all nodes in schedule sorted order.
|
|
|
|
///
|
|
|
|
void ScheduleDAG::EmitAll() {
|
|
|
|
// For each node in the ordering
|
|
|
|
for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
|
|
|
|
// Get the scheduling info
|
|
|
|
NodeInfo *NI = Ordering[i];
|
|
|
|
if (NI->isInGroup()) {
|
|
|
|
NodeGroupIterator NGI(Ordering[i]);
|
|
|
|
while (NodeInfo *NI = NGI.next()) EmitNode(NI);
|
|
|
|
} else {
|
|
|
|
EmitNode(NI);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isFlagDefiner - Returns true if the node defines a flag result.
|
|
|
|
static bool isFlagDefiner(SDNode *A) {
|
|
|
|
unsigned N = A->getNumValues();
|
|
|
|
return N && A->getValueType(N - 1) == MVT::Flag;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isFlagUser - Returns true if the node uses a flag result.
|
|
|
|
///
|
|
|
|
static bool isFlagUser(SDNode *A) {
|
|
|
|
unsigned N = A->getNumOperands();
|
|
|
|
return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// printNI - Print node info.
|
|
|
|
///
|
|
|
|
void ScheduleDAG::printNI(std::ostream &O, NodeInfo *NI) const {
|
|
|
|
#ifndef NDEBUG
|
|
|
|
SDNode *Node = NI->Node;
|
|
|
|
O << " "
|
|
|
|
<< std::hex << Node << std::dec
|
|
|
|
<< ", Lat=" << NI->Latency
|
|
|
|
<< ", Slot=" << NI->Slot
|
|
|
|
<< ", ARITY=(" << Node->getNumOperands() << ","
|
|
|
|
<< Node->getNumValues() << ")"
|
|
|
|
<< " " << Node->getOperationName(&DAG);
|
|
|
|
if (isFlagDefiner(Node)) O << "<#";
|
|
|
|
if (isFlagUser(Node)) O << ">#";
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/// printChanges - Hilight changes in order caused by scheduling.
|
|
|
|
///
|
|
|
|
void ScheduleDAG::printChanges(unsigned Index) const {
|
|
|
|
#ifndef NDEBUG
|
|
|
|
// Get the ordered node count
|
|
|
|
unsigned N = Ordering.size();
|
|
|
|
// Determine if any changes
|
|
|
|
unsigned i = 0;
|
|
|
|
for (; i < N; i++) {
|
|
|
|
NodeInfo *NI = Ordering[i];
|
|
|
|
if (NI->Preorder != i) break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i < N) {
|
|
|
|
std::cerr << Index << ". New Ordering\n";
|
|
|
|
|
|
|
|
for (i = 0; i < N; i++) {
|
|
|
|
NodeInfo *NI = Ordering[i];
|
|
|
|
std::cerr << " " << NI->Preorder << ". ";
|
|
|
|
printNI(std::cerr, NI);
|
|
|
|
std::cerr << "\n";
|
|
|
|
if (NI->isGroupDominator()) {
|
|
|
|
NodeGroup *Group = NI->Group;
|
|
|
|
for (NIIterator NII = Group->group_begin(), E = Group->group_end();
|
|
|
|
NII != E; NII++) {
|
|
|
|
std::cerr << " ";
|
|
|
|
printNI(std::cerr, *NII);
|
|
|
|
std::cerr << "\n";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
std::cerr << Index << ". No Changes\n";
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/// print - Print ordering to specified output stream.
|
|
|
|
///
|
|
|
|
void ScheduleDAG::print(std::ostream &O) const {
|
|
|
|
#ifndef NDEBUG
|
|
|
|
using namespace std;
|
|
|
|
O << "Ordering\n";
|
|
|
|
for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
|
|
|
|
NodeInfo *NI = Ordering[i];
|
|
|
|
printNI(O, NI);
|
|
|
|
O << "\n";
|
|
|
|
if (NI->isGroupDominator()) {
|
|
|
|
NodeGroup *Group = NI->Group;
|
|
|
|
for (NIIterator NII = Group->group_begin(), E = Group->group_end();
|
|
|
|
NII != E; NII++) {
|
|
|
|
O << " ";
|
|
|
|
printNI(O, *NII);
|
|
|
|
O << "\n";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2006-01-21 02:32:06 +00:00
|
|
|
void ScheduleDAG::dump(const char *tag) const {
|
|
|
|
std::cerr << tag; dump();
|
2005-09-26 21:57:04 +00:00
|
|
|
}
|
|
|
|
|
2006-01-21 02:32:06 +00:00
|
|
|
void ScheduleDAG::dump() const {
|
2005-09-26 21:57:04 +00:00
|
|
|
print(std::cerr);
|
|
|
|
}
|
|
|
|
|
2006-01-21 02:32:06 +00:00
|
|
|
/// Run - perform scheduling.
|
|
|
|
///
|
|
|
|
MachineBasicBlock *ScheduleDAG::Run() {
|
|
|
|
TII = TM.getInstrInfo();
|
|
|
|
MRI = TM.getRegisterInfo();
|
|
|
|
RegMap = BB->getParent()->getSSARegMap();
|
|
|
|
ConstPool = BB->getParent()->getConstantPool();
|
2006-01-23 07:01:07 +00:00
|
|
|
|
|
|
|
// Number the nodes
|
|
|
|
NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
|
|
|
|
// Set up minimum info for scheduling
|
|
|
|
PrepareNodeInfo();
|
|
|
|
// Construct node groups for flagged nodes
|
|
|
|
IdentifyGroups();
|
|
|
|
|
2006-01-21 02:32:06 +00:00
|
|
|
Schedule();
|
|
|
|
return BB;
|
2005-08-18 18:45:24 +00:00
|
|
|
}
|
2006-01-23 07:01:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
/// CountInternalUses - Returns the number of edges between the two nodes.
|
|
|
|
///
|
|
|
|
static unsigned CountInternalUses(NodeInfo *D, NodeInfo *U) {
|
|
|
|
unsigned N = 0;
|
|
|
|
for (unsigned M = U->Node->getNumOperands(); 0 < M--;) {
|
|
|
|
SDOperand Op = U->Node->getOperand(M);
|
|
|
|
if (Op.Val == D->Node) N++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return N;
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Add - Adds a definer and user pair to a node group.
|
|
|
|
///
|
|
|
|
void NodeGroup::Add(NodeInfo *D, NodeInfo *U) {
|
|
|
|
// Get current groups
|
|
|
|
NodeGroup *DGroup = D->Group;
|
|
|
|
NodeGroup *UGroup = U->Group;
|
|
|
|
// If both are members of groups
|
|
|
|
if (DGroup && UGroup) {
|
|
|
|
// There may have been another edge connecting
|
|
|
|
if (DGroup == UGroup) return;
|
|
|
|
// Add the pending users count
|
|
|
|
DGroup->addPending(UGroup->getPending());
|
|
|
|
// For each member of the users group
|
|
|
|
NodeGroupIterator UNGI(U);
|
|
|
|
while (NodeInfo *UNI = UNGI.next() ) {
|
|
|
|
// Change the group
|
|
|
|
UNI->Group = DGroup;
|
|
|
|
// For each member of the definers group
|
|
|
|
NodeGroupIterator DNGI(D);
|
|
|
|
while (NodeInfo *DNI = DNGI.next() ) {
|
|
|
|
// Remove internal edges
|
|
|
|
DGroup->addPending(-CountInternalUses(DNI, UNI));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// Merge the two lists
|
|
|
|
DGroup->group_insert(DGroup->group_end(),
|
|
|
|
UGroup->group_begin(), UGroup->group_end());
|
|
|
|
} else if (DGroup) {
|
|
|
|
// Make user member of definers group
|
|
|
|
U->Group = DGroup;
|
|
|
|
// Add users uses to definers group pending
|
|
|
|
DGroup->addPending(U->Node->use_size());
|
|
|
|
// For each member of the definers group
|
|
|
|
NodeGroupIterator DNGI(D);
|
|
|
|
while (NodeInfo *DNI = DNGI.next() ) {
|
|
|
|
// Remove internal edges
|
|
|
|
DGroup->addPending(-CountInternalUses(DNI, U));
|
|
|
|
}
|
|
|
|
DGroup->group_push_back(U);
|
|
|
|
} else if (UGroup) {
|
|
|
|
// Make definer member of users group
|
|
|
|
D->Group = UGroup;
|
|
|
|
// Add definers uses to users group pending
|
|
|
|
UGroup->addPending(D->Node->use_size());
|
|
|
|
// For each member of the users group
|
|
|
|
NodeGroupIterator UNGI(U);
|
|
|
|
while (NodeInfo *UNI = UNGI.next() ) {
|
|
|
|
// Remove internal edges
|
|
|
|
UGroup->addPending(-CountInternalUses(D, UNI));
|
|
|
|
}
|
|
|
|
UGroup->group_insert(UGroup->group_begin(), D);
|
|
|
|
} else {
|
|
|
|
D->Group = U->Group = DGroup = new NodeGroup();
|
|
|
|
DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
|
|
|
|
CountInternalUses(D, U));
|
|
|
|
DGroup->group_push_back(D);
|
|
|
|
DGroup->group_push_back(U);
|
|
|
|
}
|
|
|
|
}
|