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llvm-6502/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h

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Great renaming: Sparc --> SparcV9 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11826 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-25 18:44:15 +00:00
//===-- llvm/CodeGen/SparcV9InstrSelectionSupport.h ---------------*- C++ -*-===//
Added LLVM copyright header. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9321 91177308-0d34-0410-b5e6-96231b3b80d8
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//
// The LLVM Compiler Infrastructure
* Removed extraneous #includes * Fixed file headers to be consistent with the rest of LLVM * Other minor fixes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3278 91177308-0d34-0410-b5e6-96231b3b80d8
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//
Added LLVM copyright header. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9321 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-21 15:17:13 +00:00
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
* Removed extraneous #includes * Fixed file headers to be consistent with the rest of LLVM * Other minor fixes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3278 91177308-0d34-0410-b5e6-96231b3b80d8
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//
Added LLVM copyright header. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9321 91177308-0d34-0410-b5e6-96231b3b80d8
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// TODO: Need a description here.
* Removed extraneous #includes * Fixed file headers to be consistent with the rest of LLVM * Other minor fixes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3278 91177308-0d34-0410-b5e6-96231b3b80d8
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//
//===----------------------------------------------------------------------===//
Sparc-specific code shared between local files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@864 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-18 00:03:20 +00:00
#ifndef SPARC_INSTR_SELECTION_SUPPORT_h
#define SPARC_INSTR_SELECTION_SUPPORT_h
Numerous bug fixes: -- correct sign extensions for integer casts and for shift-by-constant instructions generated for integer multiply -- passing FP arguments to functions with more than 6 arguments -- passing FP arguments to varargs functions -- passing FP arguments to functions with no prototypes -- incorrect stack frame size when padding a section -- folding getelementptr operations with mixed array and struct indexes -- use uint64_t instead of uint for constant offsets in mem operands -- incorrect coloring for CC registers (both int and FP): interferences were being completely ignored for int CC and were considered but no spills were marked for fp CC! Also some code improvements: -- better interface to generating machine instr for common cases (many places still need to be updated to use this interface) -- annotations on MachineInstr to communicate information from one codegen phase to another (now used to pass information about CALL/JMPLCALL operands from selection to register allocation) -- all sizes and offests in class TargetData are uint64_t instead of uint git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2640 91177308-0d34-0410-b5e6-96231b3b80d8
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#include "llvm/DerivedTypes.h"
Great renaming: Sparc --> SparcV9 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11826 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-25 18:44:15 +00:00
#include "SparcV9Internals.h"
Sparc-specific code shared between local files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@864 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-18 00:03:20 +00:00
Put all LLVM code into the llvm namespace, as per bug 109. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-11 22:41:34 +00:00
namespace llvm {
Add comments to describe what these functions actually do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9370 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-22 05:50:40 +00:00
// Choose load instruction opcode based on type of value
Sparc-specific code shared between local files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@864 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-18 00:03:20 +00:00
inline MachineOpCode
ChooseLoadInstruction(const Type *DestTy)
{
switch (DestTy->getPrimitiveID()) {
case Type::BoolTyID:
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed. Non-obvious change: since I have changed ST and STD to be STF and STDF to (a) closer resemble their name (NOT assembly text) in the Sparc manual, and (b) clearly specify that they they are floating-point opcodes, I made the same changes in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6376 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:39:01 +00:00
case Type::UByteTyID: return V9::LDUBr;
case Type::SByteTyID: return V9::LDSBr;
case Type::UShortTyID: return V9::LDUHr;
case Type::ShortTyID: return V9::LDSHr;
case Type::UIntTyID: return V9::LDUWr;
case Type::IntTyID: return V9::LDSWr;
Sparc-specific code shared between local files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@864 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-18 00:03:20 +00:00
case Type::PointerTyID:
case Type::ULongTyID:
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed. Non-obvious change: since I have changed ST and STD to be STF and STDF to (a) closer resemble their name (NOT assembly text) in the Sparc manual, and (b) clearly specify that they they are floating-point opcodes, I made the same changes in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6376 91177308-0d34-0410-b5e6-96231b3b80d8
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case Type::LongTyID: return V9::LDXr;
case Type::FloatTyID: return V9::LDFr;
case Type::DoubleTyID: return V9::LDDFr;
Sparc-specific code shared between local files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@864 91177308-0d34-0410-b5e6-96231b3b80d8
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default: assert(0 && "Invalid type for Load instruction");
}
return 0;
}
Add comments to describe what these functions actually do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9370 91177308-0d34-0410-b5e6-96231b3b80d8
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// Choose store instruction opcode based on type of value
Sparc-specific code shared between local files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@864 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-18 00:03:20 +00:00
inline MachineOpCode
ChooseStoreInstruction(const Type *DestTy)
{
switch (DestTy->getPrimitiveID()) {
case Type::BoolTyID:
case Type::UByteTyID:
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed. Non-obvious change: since I have changed ST and STD to be STF and STDF to (a) closer resemble their name (NOT assembly text) in the Sparc manual, and (b) clearly specify that they they are floating-point opcodes, I made the same changes in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6376 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:39:01 +00:00
case Type::SByteTyID: return V9::STBr;
Sparc-specific code shared between local files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@864 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-18 00:03:20 +00:00
case Type::UShortTyID:
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed. Non-obvious change: since I have changed ST and STD to be STF and STDF to (a) closer resemble their name (NOT assembly text) in the Sparc manual, and (b) clearly specify that they they are floating-point opcodes, I made the same changes in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6376 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:39:01 +00:00
case Type::ShortTyID: return V9::STHr;
Sparc-specific code shared between local files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@864 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-18 00:03:20 +00:00
case Type::UIntTyID:
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed. Non-obvious change: since I have changed ST and STD to be STF and STDF to (a) closer resemble their name (NOT assembly text) in the Sparc manual, and (b) clearly specify that they they are floating-point opcodes, I made the same changes in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6376 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:39:01 +00:00
case Type::IntTyID: return V9::STWr;
Sparc-specific code shared between local files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@864 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-18 00:03:20 +00:00
case Type::PointerTyID:
case Type::ULongTyID:
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed. Non-obvious change: since I have changed ST and STD to be STF and STDF to (a) closer resemble their name (NOT assembly text) in the Sparc manual, and (b) clearly specify that they they are floating-point opcodes, I made the same changes in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6376 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:39:01 +00:00
case Type::LongTyID: return V9::STXr;
case Type::FloatTyID: return V9::STFr;
case Type::DoubleTyID: return V9::STDFr;
Sparc-specific code shared between local files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@864 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-18 00:03:20 +00:00
default: assert(0 && "Invalid type for Store instruction");
}
return 0;
}
Numerous bug fixes: -- correct sign extensions for integer casts and for shift-by-constant instructions generated for integer multiply -- passing FP arguments to functions with more than 6 arguments -- passing FP arguments to varargs functions -- passing FP arguments to functions with no prototypes -- incorrect stack frame size when padding a section -- folding getelementptr operations with mixed array and struct indexes -- use uint64_t instead of uint for constant offsets in mem operands -- incorrect coloring for CC registers (both int and FP): interferences were being completely ignored for int CC and were considered but no spills were marked for fp CC! Also some code improvements: -- better interface to generating machine instr for common cases (many places still need to be updated to use this interface) -- annotations on MachineInstr to communicate information from one codegen phase to another (now used to pass information about CALL/JMPLCALL operands from selection to register allocation) -- all sizes and offests in class TargetData are uint64_t instead of uint git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2640 91177308-0d34-0410-b5e6-96231b3b80d8
2002-05-19 15:25:51 +00:00
inline MachineOpCode
ChooseAddInstructionByType(const Type* resultType)
{
Sparc instruction opcodes now all live under the `V9' namespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6249 91177308-0d34-0410-b5e6-96231b3b80d8
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MachineOpCode opCode = V9::INVALID_OPCODE;
Numerous bug fixes: -- correct sign extensions for integer casts and for shift-by-constant instructions generated for integer multiply -- passing FP arguments to functions with more than 6 arguments -- passing FP arguments to varargs functions -- passing FP arguments to functions with no prototypes -- incorrect stack frame size when padding a section -- folding getelementptr operations with mixed array and struct indexes -- use uint64_t instead of uint for constant offsets in mem operands -- incorrect coloring for CC registers (both int and FP): interferences were being completely ignored for int CC and were considered but no spills were marked for fp CC! Also some code improvements: -- better interface to generating machine instr for common cases (many places still need to be updated to use this interface) -- annotations on MachineInstr to communicate information from one codegen phase to another (now used to pass information about CALL/JMPLCALL operands from selection to register allocation) -- all sizes and offests in class TargetData are uint64_t instead of uint git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2640 91177308-0d34-0410-b5e6-96231b3b80d8
2002-05-19 15:25:51 +00:00
if (resultType->isIntegral() ||
isa<PointerType>(resultType) ||
isa<FunctionType>(resultType) ||
- Renamed Type::isIntegral() to Type::isInteger() - Added new method Type::isIntegral() that is the same as isInteger, but also accepts bool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3574 91177308-0d34-0410-b5e6-96231b3b80d8
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resultType == Type::LabelTy)
Sparc instruction opcodes now all live under the `V9' namespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6249 91177308-0d34-0410-b5e6-96231b3b80d8
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{
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed. Non-obvious change: since I have changed ST and STD to be STF and STDF to (a) closer resemble their name (NOT assembly text) in the Sparc manual, and (b) clearly specify that they they are floating-point opcodes, I made the same changes in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6376 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:39:01 +00:00
opCode = V9::ADDr;
Sparc instruction opcodes now all live under the `V9' namespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6249 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-20 20:32:24 +00:00
}
Numerous bug fixes: -- correct sign extensions for integer casts and for shift-by-constant instructions generated for integer multiply -- passing FP arguments to functions with more than 6 arguments -- passing FP arguments to varargs functions -- passing FP arguments to functions with no prototypes -- incorrect stack frame size when padding a section -- folding getelementptr operations with mixed array and struct indexes -- use uint64_t instead of uint for constant offsets in mem operands -- incorrect coloring for CC registers (both int and FP): interferences were being completely ignored for int CC and were considered but no spills were marked for fp CC! Also some code improvements: -- better interface to generating machine instr for common cases (many places still need to be updated to use this interface) -- annotations on MachineInstr to communicate information from one codegen phase to another (now used to pass information about CALL/JMPLCALL operands from selection to register allocation) -- all sizes and offests in class TargetData are uint64_t instead of uint git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2640 91177308-0d34-0410-b5e6-96231b3b80d8
2002-05-19 15:25:51 +00:00
else
switch(resultType->getPrimitiveID())
Sparc instruction opcodes now all live under the `V9' namespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6249 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-20 20:32:24 +00:00
{
case Type::FloatTyID: opCode = V9::FADDS; break;
case Type::DoubleTyID: opCode = V9::FADDD; break;
default: assert(0 && "Invalid type for ADD instruction"); break;
}
Numerous bug fixes: -- correct sign extensions for integer casts and for shift-by-constant instructions generated for integer multiply -- passing FP arguments to functions with more than 6 arguments -- passing FP arguments to varargs functions -- passing FP arguments to functions with no prototypes -- incorrect stack frame size when padding a section -- folding getelementptr operations with mixed array and struct indexes -- use uint64_t instead of uint for constant offsets in mem operands -- incorrect coloring for CC registers (both int and FP): interferences were being completely ignored for int CC and were considered but no spills were marked for fp CC! Also some code improvements: -- better interface to generating machine instr for common cases (many places still need to be updated to use this interface) -- annotations on MachineInstr to communicate information from one codegen phase to another (now used to pass information about CALL/JMPLCALL operands from selection to register allocation) -- all sizes and offests in class TargetData are uint64_t instead of uint git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2640 91177308-0d34-0410-b5e6-96231b3b80d8
2002-05-19 15:25:51 +00:00
return opCode;
}
Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes. Code beautification for the rest of the code: changed layout to match the rest of the code base. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6446 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 20:11:56 +00:00
Great renaming: Sparc --> SparcV9 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11826 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-25 18:44:15 +00:00
// Because the SparcV9 instruction selector likes to re-write operands to
Add comments to describe what these functions actually do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9370 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-22 05:50:40 +00:00
// instructions, making them change from a Value* (virtual register) to a
// Constant* (making an immediate field), we need to change the opcode from a
// register-based instruction to an immediate-based instruction, hence this
// mapping.
Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes. Code beautification for the rest of the code: changed layout to match the rest of the code base. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6446 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 20:11:56 +00:00
static unsigned
convertOpcodeFromRegToImm(unsigned Opcode) {
switch (Opcode) {
/* arithmetic */
case V9::ADDr: return V9::ADDi;
case V9::ADDccr: return V9::ADDcci;
case V9::ADDCr: return V9::ADDCi;
case V9::ADDCccr: return V9::ADDCcci;
case V9::SUBr: return V9::SUBi;
case V9::SUBccr: return V9::SUBcci;
case V9::SUBCr: return V9::SUBCi;
case V9::SUBCccr: return V9::SUBCcci;
case V9::MULXr: return V9::MULXi;
case V9::SDIVXr: return V9::SDIVXi;
case V9::UDIVXr: return V9::UDIVXi;
/* logical */
case V9::ANDr: return V9::ANDi;
case V9::ANDccr: return V9::ANDcci;
case V9::ANDNr: return V9::ANDNi;
case V9::ANDNccr: return V9::ANDNcci;
case V9::ORr: return V9::ORi;
case V9::ORccr: return V9::ORcci;
case V9::ORNr: return V9::ORNi;
case V9::ORNccr: return V9::ORNcci;
case V9::XORr: return V9::XORi;
case V9::XORccr: return V9::XORcci;
case V9::XNORr: return V9::XNORi;
case V9::XNORccr: return V9::XNORcci;
/* shift */
* Changed Bcc instructions to behave like BPcc instructions * BPA and BPN do not take a %cc register as a parameter * SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions * Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit * Added WRCCR{r,i} opcodes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6655 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-06 09:52:23 +00:00
case V9::SLLr5: return V9::SLLi5;
case V9::SRLr5: return V9::SRLi5;
case V9::SRAr5: return V9::SRAi5;
Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes. Code beautification for the rest of the code: changed layout to match the rest of the code base. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6446 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 20:11:56 +00:00
case V9::SLLXr6: return V9::SLLXi6;
case V9::SRLXr6: return V9::SRLXi6;
case V9::SRAXr6: return V9::SRAXi6;
Added opcode conversion for conditional move of integers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6567 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03 03:23:35 +00:00
/* Conditional move on int comparison with zero */
case V9::MOVRZr: return V9::MOVRZi;
case V9::MOVRLEZr: return V9::MOVRLEZi;
case V9::MOVRLZr: return V9::MOVRLZi;
case V9::MOVRNZr: return V9::MOVRNZi;
case V9::MOVRGZr: return V9::MOVRGZi;
case V9::MOVRGEZr: return V9::MOVRGEZi;
/* Conditional move on int condition code */
case V9::MOVAr: return V9::MOVAi;
case V9::MOVNr: return V9::MOVNi;
case V9::MOVNEr: return V9::MOVNEi;
case V9::MOVEr: return V9::MOVEi;
case V9::MOVGr: return V9::MOVGi;
case V9::MOVLEr: return V9::MOVLEi;
case V9::MOVGEr: return V9::MOVGEi;
case V9::MOVLr: return V9::MOVLi;
case V9::MOVGUr: return V9::MOVGUi;
case V9::MOVLEUr: return V9::MOVLEUi;
case V9::MOVCCr: return V9::MOVCCi;
case V9::MOVCSr: return V9::MOVCSi;
case V9::MOVPOSr: return V9::MOVPOSi;
case V9::MOVNEGr: return V9::MOVNEGi;
case V9::MOVVCr: return V9::MOVVCi;
case V9::MOVVSr: return V9::MOVVSi;
/* Conditional move of int reg on fp condition code */
case V9::MOVFAr: return V9::MOVFAi;
case V9::MOVFNr: return V9::MOVFNi;
case V9::MOVFUr: return V9::MOVFUi;
case V9::MOVFGr: return V9::MOVFGi;
case V9::MOVFUGr: return V9::MOVFUGi;
case V9::MOVFLr: return V9::MOVFLi;
case V9::MOVFULr: return V9::MOVFULi;
case V9::MOVFLGr: return V9::MOVFLGi;
case V9::MOVFNEr: return V9::MOVFNEi;
case V9::MOVFEr: return V9::MOVFEi;
case V9::MOVFUEr: return V9::MOVFUEi;
case V9::MOVFGEr: return V9::MOVFGEi;
case V9::MOVFUGEr: return V9::MOVFUGEi;
case V9::MOVFLEr: return V9::MOVFLEi;
case V9::MOVFULEr: return V9::MOVFULEi;
case V9::MOVFOr: return V9::MOVFOi;
Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes. Code beautification for the rest of the code: changed layout to match the rest of the code base. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6446 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 20:11:56 +00:00
/* load */
case V9::LDSBr: return V9::LDSBi;
case V9::LDSHr: return V9::LDSHi;
case V9::LDSWr: return V9::LDSWi;
case V9::LDUBr: return V9::LDUBi;
case V9::LDUHr: return V9::LDUHi;
case V9::LDUWr: return V9::LDUWi;
case V9::LDXr: return V9::LDXi;
case V9::LDFr: return V9::LDFi;
case V9::LDDFr: return V9::LDDFi;
case V9::LDQFr: return V9::LDQFi;
case V9::LDFSRr: return V9::LDFSRi;
case V9::LDXFSRr: return V9::LDXFSRi;
/* store */
case V9::STBr: return V9::STBi;
case V9::STHr: return V9::STHi;
case V9::STWr: return V9::STWi;
case V9::STXr: return V9::STXi;
case V9::STFr: return V9::STFi;
case V9::STDFr: return V9::STDFi;
case V9::STFSRr: return V9::STFSRi;
case V9::STXFSRr: return V9::STXFSRi;
/* jump & return */
case V9::JMPLCALLr: return V9::JMPLCALLi;
case V9::JMPLRETr: return V9::JMPLRETi;
case V9::RETURNr: return V9::RETURNi;
/* save and restore */
case V9::SAVEr: return V9::SAVEi;
case V9::RESTOREr: return V9::RESTOREi;
default:
// It's already in correct format
Added opcode conversion for conditional move of integers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6567 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03 03:23:35 +00:00
// Or, it's just not handled yet, but an assert() would break LLC
#if 0
std::cerr << "Unhandled opcode in convertOpcodeFromRegToImm(): " << Opcode
<< "\n";
#endif
Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes. Code beautification for the rest of the code: changed layout to match the rest of the code base. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6446 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 20:11:56 +00:00
return Opcode;
}
}
Move ChooseRegOrImmed() prototype here, from InstrSelectionSupport.h. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12765 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-07 20:38:57 +00:00
MachineOperand::MachineOperandType
ChooseRegOrImmed(Value* val, MachineOpCode opCode,
const TargetMachine& targetMachine, bool canUseImmed,
unsigned& getMachineRegNum, int64_t& getImmedValue);
Put all LLVM code into the llvm namespace, as per bug 109. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-11 22:41:34 +00:00
} // End llvm namespace
Changes to build successfully with GCC 3.02 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1503 91177308-0d34-0410-b5e6-96231b3b80d8
2002-01-20 22:54:45 +00:00
#endif
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