2004-04-25 07:04:49 +00:00
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//===-- SparcV9PrologEpilogCodeInserter.cpp - Insert Fn Prolog & Epilog ---===//
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2003-10-20 19:43:21 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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2002-04-09 05:18:31 +00:00
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//
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2004-08-16 18:27:25 +00:00
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// This is the SparcV9 target's own PrologEpilogInserter. It creates prolog and
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// epilog instructions for functions which have not been compiled using "leaf
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// function optimizations". These instructions include the SAVE and RESTORE
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// instructions used to rotate the SPARC register windows. Prologs are
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// attached to the unique function entry, and epilogs are attached to each
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// function exit.
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2002-04-09 05:18:31 +00:00
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//
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//===----------------------------------------------------------------------===//
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2004-02-25 18:44:15 +00:00
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#include "SparcV9Internals.h"
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#include "SparcV9RegClassInfo.h"
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2004-08-12 17:56:01 +00:00
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#include "SparcV9RegisterInfo.h"
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#include "SparcV9FrameInfo.h"
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2004-08-16 21:55:02 +00:00
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#include "MachineFunctionInfo.h"
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#include "MachineCodeForInstruction.h"
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2002-12-28 20:16:08 +00:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2002-10-28 21:43:57 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2002-04-09 05:18:31 +00:00
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#include "llvm/Pass.h"
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#include "llvm/Function.h"
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2003-05-25 15:59:47 +00:00
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#include "llvm/DerivedTypes.h"
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#include "llvm/Intrinsics.h"
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2002-04-09 05:18:31 +00:00
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2003-11-11 22:41:34 +00:00
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namespace llvm {
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2002-04-09 05:18:31 +00:00
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namespace {
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2002-12-28 20:16:08 +00:00
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struct InsertPrologEpilogCode : public MachineFunctionPass {
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2004-02-25 18:44:15 +00:00
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const char *getPassName() const { return "SparcV9 Prolog/Epilog Inserter"; }
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2002-06-25 16:13:21 +00:00
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2002-12-28 20:16:08 +00:00
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bool runOnMachineFunction(MachineFunction &F) {
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2004-08-18 18:13:37 +00:00
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if (!F.getInfo<SparcV9FunctionInfo>()->isCompiledAsLeafMethod()) {
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2002-06-25 16:13:21 +00:00
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InsertPrologCode(F);
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InsertEpilogCode(F);
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}
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return false;
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2002-04-09 05:18:31 +00:00
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}
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2002-06-25 16:13:21 +00:00
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2002-12-28 20:16:08 +00:00
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void InsertPrologCode(MachineFunction &F);
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void InsertEpilogCode(MachineFunction &F);
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2002-06-25 16:13:21 +00:00
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};
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2002-04-09 05:18:31 +00:00
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} // End anonymous namespace
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2004-03-31 20:58:37 +00:00
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static unsigned getStaticStackSize (MachineFunction &MF) {
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2004-06-02 05:55:25 +00:00
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const TargetFrameInfo& frameInfo = *MF.getTarget().getFrameInfo();
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2004-08-18 18:13:37 +00:00
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unsigned staticStackSize = MF.getInfo<SparcV9FunctionInfo>()->getStaticStackSize();
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2004-08-12 18:36:28 +00:00
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if (staticStackSize < (unsigned)SparcV9FrameInfo::MinStackFrameSize)
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2004-08-12 18:29:05 +00:00
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staticStackSize = SparcV9FrameInfo::MinStackFrameSize;
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2004-08-12 18:20:55 +00:00
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if (unsigned padsz = staticStackSize %
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SparcV9FrameInfo::StackFrameSizeAlignment)
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staticStackSize += SparcV9FrameInfo::StackFrameSizeAlignment - padsz;
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2004-03-31 20:58:37 +00:00
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return staticStackSize;
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}
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2002-12-28 20:16:08 +00:00
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void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
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{
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2002-06-25 20:55:50 +00:00
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std::vector<MachineInstr*> mvec;
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameInfo& frameInfo = *TM.getFrameInfo();
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2002-04-09 05:18:31 +00:00
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// The second operand is the stack size. If it does not fit in the
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// immediate field, we have to use a free register to hold the size.
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2002-10-13 00:24:06 +00:00
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// See the comments below for the choice of this register.
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2004-03-31 20:58:37 +00:00
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unsigned staticStackSize = getStaticStackSize (MF);
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2002-10-28 21:43:57 +00:00
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int32_t C = - (int) staticStackSize;
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2004-06-02 05:55:25 +00:00
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int SP = TM.getRegInfo()->getStackPointer();
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if (TM.getInstrInfo()->constantFitsInImmedField(V9::SAVEi,staticStackSize)) {
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2003-05-27 22:35:43 +00:00
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mvec.push_back(BuildMI(V9::SAVEi, 3).addMReg(SP).addSImm(C)
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2004-02-22 19:23:26 +00:00
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.addMReg(SP, MachineOperand::Def));
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2002-10-28 21:43:57 +00:00
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} else {
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2002-12-28 20:16:08 +00:00
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// We have to put the stack size value into a register before SAVE.
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// Use register %g1 since it is volatile across calls. Note that the
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// local (%l) and in (%i) registers cannot be used before the SAVE!
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// Do this by creating a code sequence equivalent to:
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// SETSW -(stackSize), %g1
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2004-06-02 05:55:25 +00:00
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int uregNum = TM.getRegInfo()->getUnifiedRegNum(
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TM.getRegInfo()->getRegClassIDOfType(Type::IntTy),
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SparcV9IntRegClass::g1);
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2002-12-28 20:16:08 +00:00
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2003-05-20 20:32:24 +00:00
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MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C)
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2004-02-22 19:23:26 +00:00
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.addMReg(uregNum, MachineOperand::Def);
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2004-07-19 07:52:35 +00:00
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M->getOperand(0).markHi32();
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2002-12-28 20:16:08 +00:00
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mvec.push_back(M);
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2003-05-27 22:35:43 +00:00
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M = BuildMI(V9::ORi, 3).addMReg(uregNum).addSImm(C)
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2004-02-22 19:23:26 +00:00
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.addMReg(uregNum, MachineOperand::Def);
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2004-07-19 07:52:35 +00:00
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M->getOperand(1).markLo32();
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2002-12-28 20:16:08 +00:00
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mvec.push_back(M);
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2003-06-06 09:52:23 +00:00
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M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0)
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2004-02-22 19:23:26 +00:00
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.addMReg(uregNum, MachineOperand::Def);
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2002-12-28 20:16:08 +00:00
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mvec.push_back(M);
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// Now generate the SAVE using the value in register %g1
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2004-02-22 19:23:26 +00:00
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M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum)
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.addMReg(SP,MachineOperand::Def);
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2002-12-28 20:16:08 +00:00
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mvec.push_back(M);
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}
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2002-04-09 05:18:31 +00:00
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2003-05-25 15:59:47 +00:00
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// For varargs function bodies, insert instructions to copy incoming
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// register arguments for the ... list to the stack.
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// The first K=6 arguments are always received via int arg regs
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// (%i0 ... %i5 if K=6) .
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// By copying the varargs arguments to the stack, va_arg() then can
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// simply assume that all vararg arguments are in an array on the stack.
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if (MF.getFunction()->getFunctionType()->isVarArg()) {
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int numFixedArgs = MF.getFunction()->getFunctionType()->getNumParams();
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2004-06-02 05:55:25 +00:00
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int numArgRegs = TM.getRegInfo()->getNumOfIntArgRegs();
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2003-05-25 15:59:47 +00:00
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if (numFixedArgs < numArgRegs) {
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2004-06-02 05:55:25 +00:00
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const TargetFrameInfo &FI = *TM.getFrameInfo();
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int firstArgReg = TM.getRegInfo()->getUnifiedRegNum(
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TM.getRegInfo()->getRegClassIDOfType(Type::IntTy),
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2004-02-25 18:44:15 +00:00
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SparcV9IntRegClass::i0);
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2004-08-12 17:56:01 +00:00
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int fpReg = SparcV9::i6;
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int argSize = 8;
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int firstArgOffset= SparcV9FrameInfo::FirstIncomingArgOffsetFromFP;
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2003-05-25 15:59:47 +00:00
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int nextArgOffset = firstArgOffset + numFixedArgs * argSize;
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for (int i=numFixedArgs; i < numArgRegs; ++i) {
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2003-05-27 22:35:43 +00:00
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mvec.push_back(BuildMI(V9::STXi, 3).addMReg(firstArgReg+i).
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2003-05-25 15:59:47 +00:00
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addMReg(fpReg).addSImm(nextArgOffset));
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nextArgOffset += argSize;
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}
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}
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}
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2002-12-28 20:16:08 +00:00
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MF.front().insert(MF.front().begin(), mvec.begin(), mvec.end());
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2002-04-09 05:18:31 +00:00
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}
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2002-12-28 20:16:08 +00:00
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void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
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2002-04-09 05:18:31 +00:00
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{
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2002-12-28 20:16:08 +00:00
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const TargetMachine &TM = MF.getTarget();
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2004-06-02 05:55:25 +00:00
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const TargetInstrInfo &MII = *TM.getInstrInfo();
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2002-12-28 20:16:08 +00:00
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2002-10-28 20:01:13 +00:00
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock &MBB = *I;
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2003-07-26 23:04:00 +00:00
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const BasicBlock &BB = *I->getBasicBlock();
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const Instruction *TermInst = (Instruction*)BB.getTerminator();
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2002-04-09 05:18:31 +00:00
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if (TermInst->getOpcode() == Instruction::Ret)
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2003-05-20 20:32:24 +00:00
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{
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2004-06-02 05:55:25 +00:00
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int ZR = TM.getRegInfo()->getZeroRegNum();
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2003-05-20 20:32:24 +00:00
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MachineInstr *Restore =
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2004-02-22 19:23:26 +00:00
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BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0)
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.addMReg(ZR, MachineOperand::Def);
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2003-05-20 20:32:24 +00:00
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MachineCodeForInstruction &termMvec =
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MachineCodeForInstruction::get(TermInst);
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// Remove the NOPs in the delay slots of the return instruction
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unsigned numNOPs = 0;
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2004-02-11 20:47:34 +00:00
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while (termMvec.back()->getOpcode() == V9::NOP)
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2002-04-09 05:18:31 +00:00
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{
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2004-02-12 02:27:10 +00:00
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assert( termMvec.back() == &MBB.back());
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2003-05-20 20:32:24 +00:00
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termMvec.pop_back();
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2004-02-12 02:27:10 +00:00
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MBB.erase(&MBB.back());
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2003-05-20 20:32:24 +00:00
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++numNOPs;
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}
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2004-02-12 02:27:10 +00:00
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assert(termMvec.back() == &MBB.back());
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2002-04-09 05:18:31 +00:00
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2003-05-20 20:32:24 +00:00
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// Check that we found the right number of NOPs and have the right
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// number of instructions to replace them.
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2004-02-11 20:47:34 +00:00
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unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpcode());
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2003-05-20 20:32:24 +00:00
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assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
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assert(ndelays == 1 && "Cannot use epilog code for delay slots?");
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2002-04-09 05:18:31 +00:00
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2003-05-20 20:32:24 +00:00
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// Append the epilog code to the end of the basic block.
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MBB.push_back(Restore);
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}
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2002-04-09 05:18:31 +00:00
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}
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}
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2003-11-13 00:19:02 +00:00
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FunctionPass *createPrologEpilogInsertionPass() {
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2002-12-28 20:16:08 +00:00
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return new InsertPrologEpilogCode();
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2002-04-09 05:18:31 +00:00
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}
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2003-11-11 22:41:34 +00:00
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} // End llvm namespace
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