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llvm-6502/test/CodeGen/PowerPC/sdiv-pow2.ll

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[PowerPC] Implement BuildSDIVPow2, lower i64 pow2 sdiv using sradi PPCISelDAGToDAG contained existing code to lower i32 sdiv by a power-of-2 using srawi/addze, but did not implement the i64 case. DAGCombine now contains a callback specifically designed for this purpose (BuildSDIVPow2), and part of the logic has been moved to an implementation of that callback. Doing this lowering using BuildSDIVPow2 likely does not matter, compared to handling everything in PPCISelDAGToDAG, for the positive divisor case, but the negative divisor case, which generates an additional negation, can potentially benefit from additional folding from DAGCombine. Now, both the i32 and the i64 cases have been implemented. Fixes PR20732. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224033 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-11 18:37:52 +00:00
; RUN: llc -mcpu=ppc64 < %s | FileCheck %s
[PowerPC] Don't attempt a 64-bit pow2 division on PPC32 In r224033, in moving the signed power-of-2 division expansion into BuildSDIVPow2, I accidentally made it possible to attempt the lowering for a 64-bit division on PPC32. This later asserts. Fixes PR21928. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224758 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-23 08:38:50 +00:00
; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefix=CHECK-32 %s
[PowerPC] Implement BuildSDIVPow2, lower i64 pow2 sdiv using sradi PPCISelDAGToDAG contained existing code to lower i32 sdiv by a power-of-2 using srawi/addze, but did not implement the i64 case. DAGCombine now contains a callback specifically designed for this purpose (BuildSDIVPow2), and part of the logic has been moved to an implementation of that callback. Doing this lowering using BuildSDIVPow2 likely does not matter, compared to handling everything in PPCISelDAGToDAG, for the positive divisor case, but the negative divisor case, which generates an additional negation, can potentially benefit from additional folding from DAGCombine. Now, both the i32 and the i64 cases have been implemented. Fixes PR20732. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224033 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-11 18:37:52 +00:00
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone
define signext i32 @foo4(i32 signext %a) #0 {
entry:
%div = sdiv i32 %a, 8
ret i32 %div
; CHECK-LABEL @foo4
; CHECK: srawi [[REG1:[0-9]+]], 3, 3
; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
; CHECK: extsw 3, [[REG2]]
; CHECK: blr
}
; Function Attrs: nounwind readnone
define i64 @foo8(i64 %a) #0 {
entry:
%div = sdiv i64 %a, 8
ret i64 %div
; CHECK-LABEL @foo8
; CHECK: sradi [[REG1:[0-9]+]], 3, 3
; CHECK: addze 3, [[REG1]]
; CHECK: blr
[PowerPC] Don't attempt a 64-bit pow2 division on PPC32 In r224033, in moving the signed power-of-2 division expansion into BuildSDIVPow2, I accidentally made it possible to attempt the lowering for a 64-bit division on PPC32. This later asserts. Fixes PR21928. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224758 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-23 08:38:50 +00:00
; CHECK-32-LABEL @foo8
; CHECK-32-NOT: sradi
; CHECK-32: blr
[PowerPC] Implement BuildSDIVPow2, lower i64 pow2 sdiv using sradi PPCISelDAGToDAG contained existing code to lower i32 sdiv by a power-of-2 using srawi/addze, but did not implement the i64 case. DAGCombine now contains a callback specifically designed for this purpose (BuildSDIVPow2), and part of the logic has been moved to an implementation of that callback. Doing this lowering using BuildSDIVPow2 likely does not matter, compared to handling everything in PPCISelDAGToDAG, for the positive divisor case, but the negative divisor case, which generates an additional negation, can potentially benefit from additional folding from DAGCombine. Now, both the i32 and the i64 cases have been implemented. Fixes PR20732. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224033 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-11 18:37:52 +00:00
}
; Function Attrs: nounwind readnone
define signext i32 @foo4n(i32 signext %a) #0 {
entry:
%div = sdiv i32 %a, -8
ret i32 %div
; CHECK-LABEL: @foo4n
; CHECK: srawi [[REG1:[0-9]+]], 3, 3
; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
; CHECK: neg [[REG3:[0-9]+]], [[REG2]]
; CHECK: extsw 3, [[REG3]]
; CHECK: blr
}
; Function Attrs: nounwind readnone
define i64 @foo8n(i64 %a) #0 {
entry:
%div = sdiv i64 %a, -8
ret i64 %div
; CHECK-LABEL: @foo8n
; CHECK: sradi [[REG1:[0-9]+]], 3, 3
; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
; CHECK: neg 3, [[REG2]]
; CHECK: blr
[PowerPC] Don't attempt a 64-bit pow2 division on PPC32 In r224033, in moving the signed power-of-2 division expansion into BuildSDIVPow2, I accidentally made it possible to attempt the lowering for a 64-bit division on PPC32. This later asserts. Fixes PR21928. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224758 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-23 08:38:50 +00:00
; CHECK-32-LABEL @foo8n
; CHECK-32-NOT: sradi
; CHECK-32: blr
[PowerPC] Implement BuildSDIVPow2, lower i64 pow2 sdiv using sradi PPCISelDAGToDAG contained existing code to lower i32 sdiv by a power-of-2 using srawi/addze, but did not implement the i64 case. DAGCombine now contains a callback specifically designed for this purpose (BuildSDIVPow2), and part of the logic has been moved to an implementation of that callback. Doing this lowering using BuildSDIVPow2 likely does not matter, compared to handling everything in PPCISelDAGToDAG, for the positive divisor case, but the negative divisor case, which generates an additional negation, can potentially benefit from additional folding from DAGCombine. Now, both the i32 and the i64 cases have been implemented. Fixes PR20732. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224033 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-11 18:37:52 +00:00
}
attributes #0 = { nounwind readnone }
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