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775294d183
In r224033, in moving the signed power-of-2 division expansion into BuildSDIVPow2, I accidentally made it possible to attempt the lowering for a 64-bit division on PPC32. This later asserts. Fixes PR21928. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224758 91177308-0d34-0410-b5e6-96231b3b80d8
68 lines
1.4 KiB
LLVM
68 lines
1.4 KiB
LLVM
; RUN: llc -mcpu=ppc64 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefix=CHECK-32 %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind readnone
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define signext i32 @foo4(i32 signext %a) #0 {
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entry:
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%div = sdiv i32 %a, 8
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ret i32 %div
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; CHECK-LABEL @foo4
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; CHECK: srawi [[REG1:[0-9]+]], 3, 3
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; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
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; CHECK: extsw 3, [[REG2]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define i64 @foo8(i64 %a) #0 {
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entry:
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%div = sdiv i64 %a, 8
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ret i64 %div
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; CHECK-LABEL @foo8
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; CHECK: sradi [[REG1:[0-9]+]], 3, 3
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; CHECK: addze 3, [[REG1]]
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; CHECK: blr
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; CHECK-32-LABEL @foo8
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; CHECK-32-NOT: sradi
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; CHECK-32: blr
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}
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; Function Attrs: nounwind readnone
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define signext i32 @foo4n(i32 signext %a) #0 {
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entry:
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%div = sdiv i32 %a, -8
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ret i32 %div
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; CHECK-LABEL: @foo4n
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; CHECK: srawi [[REG1:[0-9]+]], 3, 3
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; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
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; CHECK: neg [[REG3:[0-9]+]], [[REG2]]
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; CHECK: extsw 3, [[REG3]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define i64 @foo8n(i64 %a) #0 {
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entry:
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%div = sdiv i64 %a, -8
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ret i64 %div
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; CHECK-LABEL: @foo8n
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; CHECK: sradi [[REG1:[0-9]+]], 3, 3
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; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
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; CHECK: neg 3, [[REG2]]
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; CHECK: blr
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; CHECK-32-LABEL @foo8n
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; CHECK-32-NOT: sradi
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; CHECK-32: blr
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}
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attributes #0 = { nounwind readnone }
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