2008-12-08 17:50:35 +00:00
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//===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
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2008-11-19 23:18:57 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2008-12-08 17:50:35 +00:00
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// This implements the ScheduleDAGInstrs class, which implements re-scheduling
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// of MachineInstrs.
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2008-11-19 23:18:57 +00:00
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched-instrs"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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2008-12-04 01:35:46 +00:00
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#include "llvm/CodeGen/PseudoSourceValue.h"
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2008-11-19 23:18:57 +00:00
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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2008-12-04 01:35:46 +00:00
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#include <map>
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2008-11-19 23:18:57 +00:00
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using namespace llvm;
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ScheduleDAGInstrs::ScheduleDAGInstrs(MachineBasicBlock *bb,
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const TargetMachine &tm)
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: ScheduleDAG(0, bb, tm) {}
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void ScheduleDAGInstrs::BuildSchedUnits() {
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SUnits.clear();
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SUnits.reserve(BB->size());
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2008-12-04 01:35:46 +00:00
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// We build scheduling units by walking a block's instruction list from bottom
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// to top.
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// Remember where defs and uses of each physical register are as we procede.
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2008-11-19 23:18:57 +00:00
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SUnit *Defs[TargetRegisterInfo::FirstVirtualRegister] = {};
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std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister] = {};
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2008-12-04 01:35:46 +00:00
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// Remember where unknown loads are after the most recent unknown store
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// as we procede.
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std::vector<SUnit *> PendingLoads;
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// Remember where a generic side-effecting instruction is as we procede. If
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// ChainMMO is null, this is assumed to have arbitrary side-effects. If
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// ChainMMO is non-null, then Chain makes only a single memory reference.
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SUnit *Chain = 0;
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MachineMemOperand *ChainMMO = 0;
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// Memory references to specific known memory locations are tracked so that
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// they can be given more precise dependencies.
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std::map<const Value *, SUnit *> MemDefs;
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std::map<const Value *, std::vector<SUnit *> > MemUses;
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// Terminators can perform control transfers, we we need to make sure that
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// all the work of the block is done before the terminator.
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SUnit *Terminator = 0;
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2008-11-19 23:18:57 +00:00
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for (MachineBasicBlock::iterator MII = BB->end(), MIE = BB->begin();
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MII != MIE; --MII) {
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MachineInstr *MI = prior(MII);
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SUnit *SU = NewSUnit(MI);
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2008-12-09 22:54:47 +00:00
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// Assign the Latency field of SU using target-provided information.
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ComputeLatency(SU);
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2008-12-04 01:35:46 +00:00
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// Add register-based dependencies (data, anti, and output).
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2008-11-19 23:18:57 +00:00
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for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
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const MachineOperand &MO = MI->getOperand(j);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
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std::vector<SUnit *> &UseList = Uses[Reg];
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SUnit *&Def = Defs[Reg];
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2008-11-21 19:16:58 +00:00
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// Optionally add output and anti dependencies.
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2008-12-09 22:54:47 +00:00
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// TODO: Using a latency of 1 here assumes there's no cost for
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// reusing registers.
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SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
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if (Def && Def != SU)
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Def->addPred(SDep(SU, Kind, /*Latency=*/1, /*Reg=*/Reg));
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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SUnit *&Def = Defs[*Alias];
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if (Def && Def != SU)
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2008-12-09 22:54:47 +00:00
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Def->addPred(SDep(SU, Kind, /*Latency=*/1, /*Reg=*/ *Alias));
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2008-11-19 23:18:57 +00:00
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}
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if (MO.isDef()) {
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// Add any data dependencies.
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for (unsigned i = 0, e = UseList.size(); i != e; ++i)
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if (UseList[i] != SU)
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UseList[i]->addPred(SDep(SU, SDep::Data, SU->Latency, Reg));
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &UseList = Uses[*Alias];
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for (unsigned i = 0, e = UseList.size(); i != e; ++i)
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if (UseList[i] != SU)
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UseList[i]->addPred(SDep(SU, SDep::Data, SU->Latency, *Alias));
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2008-11-19 23:18:57 +00:00
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}
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UseList.clear();
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Def = SU;
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} else {
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UseList.push_back(SU);
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}
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}
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2008-12-04 01:35:46 +00:00
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// Add chain dependencies.
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// Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
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// after stack slots are lowered to actual addresses.
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// TODO: Use an AliasAnalysis and do real alias-analysis queries, and
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// produce more precise dependence information.
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.isCall() || TID.isReturn() || TID.isBranch() ||
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TID.hasUnmodeledSideEffects()) {
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new_chain:
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2008-12-08 17:50:35 +00:00
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// This is the conservative case. Add dependencies on all memory
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// references.
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2008-11-19 23:18:57 +00:00
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if (Chain)
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Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
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Chain = SU;
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2008-11-19 23:18:57 +00:00
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for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
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PendingLoads[k]->addPred(SDep(SU, SDep::Order, SU->Latency));
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2008-11-19 23:18:57 +00:00
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PendingLoads.clear();
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2008-12-04 01:35:46 +00:00
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for (std::map<const Value *, SUnit *>::iterator I = MemDefs.begin(),
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E = MemDefs.end(); I != E; ++I) {
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I->second->addPred(SDep(SU, SDep::Order, SU->Latency));
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I->second = SU;
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}
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for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
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MemUses.begin(), E = MemUses.end(); I != E; ++I) {
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for (unsigned i = 0, e = I->second.size(); i != e; ++i)
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I->second[i]->addPred(SDep(SU, SDep::Order, SU->Latency));
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2008-12-04 01:35:46 +00:00
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I->second.clear();
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}
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// See if it is known to just have a single memory reference.
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MachineInstr *ChainMI = Chain->getInstr();
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const TargetInstrDesc &ChainTID = ChainMI->getDesc();
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if (!ChainTID.isCall() && !ChainTID.isReturn() && !ChainTID.isBranch() &&
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!ChainTID.hasUnmodeledSideEffects() &&
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ChainMI->hasOneMemOperand() &&
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!ChainMI->memoperands_begin()->isVolatile() &&
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ChainMI->memoperands_begin()->getValue())
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// We know that the Chain accesses one specific memory location.
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ChainMMO = &*ChainMI->memoperands_begin();
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else
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// Unknown memory accesses. Assume the worst.
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ChainMMO = 0;
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} else if (TID.mayStore()) {
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if (MI->hasOneMemOperand() &&
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MI->memoperands_begin()->getValue() &&
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!MI->memoperands_begin()->isVolatile() &&
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isa<PseudoSourceValue>(MI->memoperands_begin()->getValue())) {
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// A store to a specific PseudoSourceValue. Add precise dependencies.
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const Value *V = MI->memoperands_begin()->getValue();
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// Handle the def in MemDefs, if there is one.
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std::map<const Value *, SUnit *>::iterator I = MemDefs.find(V);
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if (I != MemDefs.end()) {
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2008-12-09 22:54:47 +00:00
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I->second->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0,
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/*isNormalMemory=*/true));
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2008-12-04 01:35:46 +00:00
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I->second = SU;
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} else {
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MemDefs[V] = SU;
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}
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// Handle the uses in MemUses, if there are any.
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2008-12-08 17:50:35 +00:00
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std::map<const Value *, std::vector<SUnit *> >::iterator J =
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MemUses.find(V);
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2008-12-04 01:35:46 +00:00
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if (J != MemUses.end()) {
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for (unsigned i = 0, e = J->second.size(); i != e; ++i)
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2008-12-09 22:54:47 +00:00
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J->second[i]->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0,
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/*isNormalMemory=*/true));
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2008-12-04 01:35:46 +00:00
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J->second.clear();
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}
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// Add a general dependence too, if needed.
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if (Chain)
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2008-12-09 22:54:47 +00:00
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Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
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2008-12-04 01:35:46 +00:00
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} else
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// Treat all other stores conservatively.
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goto new_chain;
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} else if (TID.mayLoad()) {
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if (TII->isInvariantLoad(MI)) {
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// Invariant load, no chain dependencies needed!
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} else if (MI->hasOneMemOperand() &&
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MI->memoperands_begin()->getValue() &&
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!MI->memoperands_begin()->isVolatile() &&
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isa<PseudoSourceValue>(MI->memoperands_begin()->getValue())) {
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// A load from a specific PseudoSourceValue. Add precise dependencies.
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const Value *V = MI->memoperands_begin()->getValue();
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std::map<const Value *, SUnit *>::iterator I = MemDefs.find(V);
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if (I != MemDefs.end())
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2008-12-09 22:54:47 +00:00
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I->second->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0,
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/*isNormalMemory=*/true));
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2008-12-04 01:35:46 +00:00
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MemUses[V].push_back(SU);
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// Add a general dependence too, if needed.
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if (Chain && (!ChainMMO ||
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(ChainMMO->isStore() || ChainMMO->isVolatile())))
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2008-12-09 22:54:47 +00:00
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Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
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2008-12-04 01:35:46 +00:00
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} else if (MI->hasVolatileMemoryRef()) {
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// Treat volatile loads conservatively. Note that this includes
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// cases where memoperand information is unavailable.
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goto new_chain;
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} else {
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// A normal load. Just depend on the general chain.
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if (Chain)
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Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
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2008-12-04 01:35:46 +00:00
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PendingLoads.push_back(SU);
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}
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2008-11-19 23:18:57 +00:00
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}
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2008-12-04 01:35:46 +00:00
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2008-12-08 17:50:35 +00:00
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// Add chain edges from the terminator to ensure that all the work of the
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// block is completed before any control transfers.
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2008-11-19 23:18:57 +00:00
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if (Terminator && SU->Succs.empty())
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Terminator->addPred(SDep(SU, SDep::Order, SU->Latency));
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2008-12-04 01:35:46 +00:00
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if (TID.isTerminator() || MI->isLabel())
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Terminator = SU;
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}
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}
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2008-11-21 00:12:10 +00:00
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void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
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const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
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// Compute the latency for the node. We use the sum of the latencies for
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// all nodes flagged together into this SUnit.
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SU->Latency =
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InstrItins.getLatency(SU->getInstr()->getDesc().getSchedClass());
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}
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2008-11-19 23:18:57 +00:00
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void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
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SU->getInstr()->dump();
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}
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std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
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std::string s;
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raw_string_ostream oss(s);
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SU->getInstr()->print(oss);
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return oss.str();
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}
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// EmitSchedule - Emit the machine code in scheduled order.
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MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
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// For MachineInstr-based scheduling, we're rescheduling the instructions in
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// the block, so start by removing them from the block.
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while (!BB->empty())
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BB->remove(BB->begin());
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for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
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SUnit *SU = Sequence[i];
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if (!SU) {
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// Null SUnit* is a noop.
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EmitNoop();
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continue;
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}
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BB->push_back(SU->getInstr());
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}
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return BB;
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}
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