2011-04-15 21:00:26 +00:00
|
|
|
//===- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
|
2007-06-06 07:42:06 +00:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 20:36:04 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2007-06-06 07:42:06 +00:00
|
|
|
//
|
2011-04-15 21:00:26 +00:00
|
|
|
//===---------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
//
|
|
|
|
// This file contains the Mips implementation of the TargetInstrInfo class.
|
|
|
|
//
|
2011-04-15 21:00:26 +00:00
|
|
|
//===---------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
#ifndef MIPSINSTRUCTIONINFO_H
|
|
|
|
#define MIPSINSTRUCTIONINFO_H
|
|
|
|
|
|
|
|
#include "Mips.h"
|
2009-07-11 20:10:48 +00:00
|
|
|
#include "llvm/Support/ErrorHandling.h"
|
2007-06-06 07:42:06 +00:00
|
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
|
|
|
#include "MipsRegisterInfo.h"
|
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
|
2007-08-18 01:59:45 +00:00
|
|
|
namespace Mips {
|
|
|
|
|
2008-07-28 19:11:24 +00:00
|
|
|
// Mips Branch Codes
|
|
|
|
enum FPBranchCode {
|
|
|
|
BRANCH_F,
|
|
|
|
BRANCH_T,
|
|
|
|
BRANCH_FL,
|
|
|
|
BRANCH_TL,
|
|
|
|
BRANCH_INVALID
|
|
|
|
};
|
|
|
|
|
2007-08-28 05:06:17 +00:00
|
|
|
// Mips Condition Codes
|
2007-08-18 01:59:45 +00:00
|
|
|
enum CondCode {
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// To be used with float branch True
|
|
|
|
FCOND_F,
|
|
|
|
FCOND_UN,
|
2011-03-31 18:26:17 +00:00
|
|
|
FCOND_OEQ,
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
FCOND_UEQ,
|
|
|
|
FCOND_OLT,
|
|
|
|
FCOND_ULT,
|
|
|
|
FCOND_OLE,
|
|
|
|
FCOND_ULE,
|
|
|
|
FCOND_SF,
|
|
|
|
FCOND_NGLE,
|
|
|
|
FCOND_SEQ,
|
|
|
|
FCOND_NGL,
|
|
|
|
FCOND_LT,
|
|
|
|
FCOND_NGE,
|
|
|
|
FCOND_LE,
|
|
|
|
FCOND_NGT,
|
|
|
|
|
|
|
|
// To be used with float branch False
|
|
|
|
// This conditions have the same mnemonic as the
|
|
|
|
// above ones, but are used with a branch False;
|
|
|
|
FCOND_T,
|
|
|
|
FCOND_OR,
|
2011-03-31 18:26:17 +00:00
|
|
|
FCOND_UNE,
|
|
|
|
FCOND_ONE,
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
FCOND_UGE,
|
|
|
|
FCOND_OGE,
|
|
|
|
FCOND_UGT,
|
|
|
|
FCOND_OGT,
|
|
|
|
FCOND_ST,
|
|
|
|
FCOND_GLE,
|
|
|
|
FCOND_SNE,
|
|
|
|
FCOND_GL,
|
|
|
|
FCOND_NLT,
|
|
|
|
FCOND_GE,
|
|
|
|
FCOND_NLE,
|
2011-04-01 17:39:08 +00:00
|
|
|
FCOND_GT
|
2007-08-18 01:59:45 +00:00
|
|
|
};
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
/// GetOppositeBranchOpc - Return the inverse of the specified
|
|
|
|
/// opcode, e.g. turning BEQ to BNE.
|
|
|
|
unsigned GetOppositeBranchOpc(unsigned Opc);
|
2007-08-18 01:59:45 +00:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
/// MipsCCToString - Map each FP condition code to its string
|
2011-03-04 17:51:39 +00:00
|
|
|
inline static const char *MipsFCCToString(Mips::CondCode CC)
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
{
|
|
|
|
switch (CC) {
|
2009-07-14 16:55:14 +00:00
|
|
|
default: llvm_unreachable("Unknown condition code");
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
case FCOND_F:
|
|
|
|
case FCOND_T: return "f";
|
|
|
|
case FCOND_UN:
|
|
|
|
case FCOND_OR: return "un";
|
2011-03-31 18:26:17 +00:00
|
|
|
case FCOND_OEQ:
|
|
|
|
case FCOND_UNE: return "eq";
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
case FCOND_UEQ:
|
2011-03-31 18:26:17 +00:00
|
|
|
case FCOND_ONE: return "ueq";
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
case FCOND_OLT:
|
|
|
|
case FCOND_UGE: return "olt";
|
|
|
|
case FCOND_ULT:
|
|
|
|
case FCOND_OGE: return "ult";
|
|
|
|
case FCOND_OLE:
|
|
|
|
case FCOND_UGT: return "ole";
|
|
|
|
case FCOND_ULE:
|
|
|
|
case FCOND_OGT: return "ule";
|
|
|
|
case FCOND_SF:
|
|
|
|
case FCOND_ST: return "sf";
|
|
|
|
case FCOND_NGLE:
|
|
|
|
case FCOND_GLE: return "ngle";
|
|
|
|
case FCOND_SEQ:
|
|
|
|
case FCOND_SNE: return "seq";
|
|
|
|
case FCOND_NGL:
|
|
|
|
case FCOND_GL: return "ngl";
|
|
|
|
case FCOND_LT:
|
|
|
|
case FCOND_NLT: return "lt";
|
|
|
|
case FCOND_NGE:
|
2011-03-31 18:26:17 +00:00
|
|
|
case FCOND_GE: return "nge";
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
case FCOND_LE:
|
2011-03-31 18:26:17 +00:00
|
|
|
case FCOND_NLE: return "le";
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
case FCOND_NGT:
|
2011-03-31 18:26:17 +00:00
|
|
|
case FCOND_GT: return "ngt";
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
}
|
|
|
|
}
|
2007-08-18 01:59:45 +00:00
|
|
|
}
|
|
|
|
|
2009-09-01 17:27:58 +00:00
|
|
|
/// MipsII - This namespace holds all of the target specific flags that
|
|
|
|
/// instruction info tracks.
|
|
|
|
///
|
|
|
|
namespace MipsII {
|
|
|
|
/// Target Operand Flag enum.
|
|
|
|
enum TOF {
|
2011-04-15 21:00:26 +00:00
|
|
|
//===-----------------------------------------------------------------===//
|
2009-09-01 17:27:58 +00:00
|
|
|
// Mips Specific MachineOperand flags.
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2009-10-05 15:52:08 +00:00
|
|
|
MO_NO_FLAG,
|
2009-09-01 17:27:58 +00:00
|
|
|
|
|
|
|
/// MO_GOT - Represents the offset into the global offset table at which
|
|
|
|
/// the address the relocation entry symbol resides during execution.
|
2009-10-05 15:52:08 +00:00
|
|
|
MO_GOT,
|
2009-09-01 17:27:58 +00:00
|
|
|
|
2011-03-04 17:51:39 +00:00
|
|
|
/// MO_GOT_CALL - Represents the offset into the global offset table at
|
|
|
|
/// which the address of a call site relocation entry symbol resides
|
2009-09-01 17:27:58 +00:00
|
|
|
/// during execution. This is different from the above since this flag
|
|
|
|
/// can only be present in call instructions.
|
2009-10-05 15:52:08 +00:00
|
|
|
MO_GOT_CALL,
|
2009-09-01 17:27:58 +00:00
|
|
|
|
2011-03-04 17:51:39 +00:00
|
|
|
/// MO_GPREL - Represents the offset from the current gp value to be used
|
2009-09-01 17:27:58 +00:00
|
|
|
/// for the relocatable object file being produced.
|
2009-10-05 15:52:08 +00:00
|
|
|
MO_GPREL,
|
2009-09-01 17:27:58 +00:00
|
|
|
|
2011-04-01 21:41:06 +00:00
|
|
|
/// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
|
2011-03-04 17:51:39 +00:00
|
|
|
/// address.
|
2011-04-01 21:41:06 +00:00
|
|
|
MO_ABS_HI,
|
|
|
|
MO_ABS_LO
|
2009-09-01 17:27:58 +00:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2008-01-01 01:03:04 +00:00
|
|
|
class MipsInstrInfo : public TargetInstrInfoImpl {
|
2007-06-06 07:42:06 +00:00
|
|
|
MipsTargetMachine &TM;
|
|
|
|
const MipsRegisterInfo RI;
|
|
|
|
public:
|
2008-03-25 22:06:05 +00:00
|
|
|
explicit MipsInstrInfo(MipsTargetMachine &TM);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
|
|
|
/// such, whenever a client has an instance of instruction info, it should
|
|
|
|
/// always be able to get register info as well (through this method).
|
|
|
|
///
|
2008-05-14 01:58:56 +00:00
|
|
|
virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
/// isLoadFromStackSlot - If the specified machine instruction is a direct
|
|
|
|
/// load from a stack slot, return the virtual or physical register number of
|
|
|
|
/// the destination along with the FrameIndex of the loaded stack slot. If
|
|
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
|
|
/// any side effects other than loading from the stack slot.
|
2008-11-18 19:49:32 +00:00
|
|
|
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
|
|
|
|
int &FrameIndex) const;
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
/// isStoreToStackSlot - If the specified machine instruction is a direct
|
|
|
|
/// store to a stack slot, return the virtual or physical register number of
|
|
|
|
/// the source reg along with the FrameIndex of the loaded stack slot. If
|
|
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
|
|
/// any side effects other than storing to the stack slot.
|
2008-11-18 19:49:32 +00:00
|
|
|
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
|
|
|
|
int &FrameIndex) const;
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2007-08-18 01:59:45 +00:00
|
|
|
/// Branch Analysis
|
|
|
|
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|
|
|
MachineBasicBlock *&FBB,
|
2009-02-09 07:14:22 +00:00
|
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
|
|
|
bool AllowModify) const;
|
2007-08-18 01:59:45 +00:00
|
|
|
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
2011-04-01 17:39:08 +00:00
|
|
|
|
|
|
|
private:
|
|
|
|
void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
|
|
|
|
const SmallVectorImpl<MachineOperand>& Cond) const;
|
|
|
|
|
|
|
|
public:
|
2007-06-06 07:42:06 +00:00
|
|
|
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
2007-08-18 01:59:45 +00:00
|
|
|
MachineBasicBlock *FBB,
|
2010-06-17 22:43:56 +00:00
|
|
|
const SmallVectorImpl<MachineOperand> &Cond,
|
|
|
|
DebugLoc DL) const;
|
2010-07-11 01:08:31 +00:00
|
|
|
virtual void copyPhysReg(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MI, DebugLoc DL,
|
|
|
|
unsigned DestReg, unsigned SrcReg,
|
|
|
|
bool KillSrc) const;
|
2008-01-01 21:11:32 +00:00
|
|
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MBBI,
|
2011-04-15 21:00:26 +00:00
|
|
|
unsigned SrcReg, bool isKill,
|
|
|
|
int FrameIndex,
|
2010-05-06 19:06:44 +00:00
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
const TargetRegisterInfo *TRI) const;
|
2008-01-01 21:11:32 +00:00
|
|
|
|
|
|
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MBBI,
|
|
|
|
unsigned DestReg, int FrameIndex,
|
2010-05-06 19:06:44 +00:00
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
const TargetRegisterInfo *TRI) const;
|
2008-01-01 21:11:32 +00:00
|
|
|
|
2008-08-14 22:49:33 +00:00
|
|
|
virtual
|
|
|
|
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
2007-08-18 01:59:45 +00:00
|
|
|
|
|
|
|
/// Insert nop instruction when hazard condition is found
|
2011-03-04 17:51:39 +00:00
|
|
|
virtual void insertNoop(MachineBasicBlock &MBB,
|
2007-08-18 01:59:45 +00:00
|
|
|
MachineBasicBlock::iterator MI) const;
|
2009-06-03 20:30:14 +00:00
|
|
|
|
|
|
|
/// getGlobalBaseReg - Return a virtual register initialized with the
|
|
|
|
/// the global base register value. Output instructions required to
|
|
|
|
/// initialize the register in the function entry block, if necessary.
|
|
|
|
///
|
|
|
|
unsigned getGlobalBaseReg(MachineFunction *MF) const;
|
2007-06-06 07:42:06 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|