2006-05-11 23:55:42 +00:00
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//===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Evan Cheng and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements bottom-up and top-down register pressure reduction list
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// schedulers, using standard algorithms. The basic approach uses a priority
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// queue of available nodes to schedule. One at a time, nodes are taken from
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// the priority queue (thus in priority order), checked for legality to
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// schedule, and emitted if legal.
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//
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//===----------------------------------------------------------------------===//
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2007-07-13 17:13:54 +00:00
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#define DEBUG_TYPE "pre-RA-sched"
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2006-05-11 23:55:42 +00:00
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#include "llvm/CodeGen/ScheduleDAG.h"
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2006-08-02 12:30:23 +00:00
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#include "llvm/CodeGen/SchedulerRegistry.h"
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2006-05-11 23:55:42 +00:00
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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2006-05-12 06:33:49 +00:00
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#include "llvm/Target/TargetData.h"
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2006-05-11 23:55:42 +00:00
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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2006-08-27 12:54:02 +00:00
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#include "llvm/Support/Compiler.h"
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2007-09-27 18:46:06 +00:00
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#include "llvm/ADT/SmallPtrSet.h"
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2007-09-25 01:54:36 +00:00
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#include "llvm/ADT/SmallSet.h"
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2006-05-11 23:55:42 +00:00
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#include "llvm/ADT/Statistic.h"
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#include <climits>
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#include <queue>
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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2007-09-27 07:09:03 +00:00
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STATISTIC(NumBacktracks, "Number of times scheduler backtraced");
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STATISTIC(NumDups, "Number of duplicated nodes");
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STATISTIC(NumCCCopies, "Number of cross class copies");
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2006-08-01 14:21:23 +00:00
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static RegisterScheduler
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burrListDAGScheduler("list-burr",
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" Bottom-up register reduction list scheduling",
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createBURRListDAGScheduler);
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static RegisterScheduler
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tdrListrDAGScheduler("list-tdrr",
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" Top-down register reduction list scheduling",
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createTDRRListDAGScheduler);
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2006-05-11 23:55:42 +00:00
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namespace {
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//===----------------------------------------------------------------------===//
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/// ScheduleDAGRRList - The actual register reduction list scheduler
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/// implementation. This supports both top-down and bottom-up scheduling.
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///
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2006-06-28 22:17:39 +00:00
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class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG {
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2006-05-11 23:55:42 +00:00
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private:
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/// isBottomUp - This is true if the scheduling problem is bottom-up, false if
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/// it is top-down.
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bool isBottomUp;
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/// AvailableQueue - The priority queue to use for the available SUnits.
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2007-09-25 01:54:36 +00:00
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///a
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2006-05-11 23:55:42 +00:00
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SchedulingPriorityQueue *AvailableQueue;
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2007-09-25 01:54:36 +00:00
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/// LiveRegs / LiveRegDefs - A set of physical registers and their definition
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/// that are "live". These nodes must be scheduled before any other nodes that
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/// modifies the registers can be scheduled.
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SmallSet<unsigned, 4> LiveRegs;
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std::vector<SUnit*> LiveRegDefs;
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std::vector<unsigned> LiveRegCycles;
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2006-05-11 23:55:42 +00:00
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public:
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ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb,
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const TargetMachine &tm, bool isbottomup,
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SchedulingPriorityQueue *availqueue)
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: ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup),
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AvailableQueue(availqueue) {
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}
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~ScheduleDAGRRList() {
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delete AvailableQueue;
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}
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void Schedule();
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private:
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2007-09-26 21:36:17 +00:00
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void ReleasePred(SUnit*, bool, unsigned);
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void ReleaseSucc(SUnit*, bool isChain, unsigned);
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void CapturePred(SUnit*, SUnit*, bool);
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void ScheduleNodeBottomUp(SUnit*, unsigned);
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void ScheduleNodeTopDown(SUnit*, unsigned);
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void UnscheduleNodeBottomUp(SUnit*);
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void BacktrackBottomUp(SUnit*, unsigned, unsigned&);
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SUnit *CopyAndMoveSuccessors(SUnit*);
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2007-09-27 07:09:03 +00:00
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void InsertCCCopiesAndMoveSuccs(SUnit*, unsigned,
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const TargetRegisterClass*,
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2007-09-26 21:36:17 +00:00
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const TargetRegisterClass*,
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2007-09-27 07:09:03 +00:00
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SmallVector<SUnit*, 2>&);
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bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&);
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2006-05-11 23:55:42 +00:00
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void ListScheduleTopDown();
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void ListScheduleBottomUp();
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2006-05-12 01:58:24 +00:00
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void CommuteNodesToReducePressure();
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2006-05-11 23:55:42 +00:00
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};
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} // end anonymous namespace
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/// Schedule - Schedule the DAG using list scheduling.
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void ScheduleDAGRRList::Schedule() {
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2006-12-07 20:04:42 +00:00
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DOUT << "********** List Scheduling **********\n";
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2007-09-25 01:54:36 +00:00
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LiveRegDefs.resize(MRI->getNumRegs(), NULL);
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LiveRegCycles.resize(MRI->getNumRegs(), 0);
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2006-05-11 23:55:42 +00:00
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// Build scheduling units.
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BuildSchedUnits();
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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2006-08-17 00:09:56 +00:00
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SUnits[su].dumpAll(&DAG));
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2006-10-14 08:34:06 +00:00
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CalculateDepths();
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CalculateHeights();
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2006-05-11 23:55:42 +00:00
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2006-11-04 09:44:31 +00:00
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AvailableQueue->initNodes(SUnitMap, SUnits);
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2007-08-20 19:28:38 +00:00
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2006-05-11 23:55:42 +00:00
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// Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
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if (isBottomUp)
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ListScheduleBottomUp();
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else
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ListScheduleTopDown();
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AvailableQueue->releaseState();
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2007-08-20 19:28:38 +00:00
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2006-05-25 08:37:31 +00:00
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CommuteNodesToReducePressure();
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2006-05-11 23:55:42 +00:00
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2006-12-07 20:04:42 +00:00
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DOUT << "*** Final schedule ***\n";
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2006-05-11 23:55:42 +00:00
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DEBUG(dumpSchedule());
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2006-12-07 20:04:42 +00:00
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DOUT << "\n";
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2006-05-11 23:55:42 +00:00
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// Emit in scheduled order
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EmitSchedule();
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}
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2006-11-04 09:44:31 +00:00
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/// CommuteNodesToReducePressure - If a node is two-address and commutable, and
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2006-05-12 01:58:24 +00:00
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/// it is not the last use of its first operand, add it to the CommuteSet if
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/// possible. It will be commuted when it is translated to a MI.
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void ScheduleDAGRRList::CommuteNodesToReducePressure() {
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2007-06-22 01:35:51 +00:00
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SmallPtrSet<SUnit*, 4> OperandSeen;
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2006-05-12 01:58:24 +00:00
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for (unsigned i = Sequence.size()-1; i != 0; --i) { // Ignore first node.
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SUnit *SU = Sequence[i];
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2007-09-26 21:36:17 +00:00
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if (!SU || !SU->Node) continue;
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2006-11-04 09:44:31 +00:00
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if (SU->isCommutable) {
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unsigned Opc = SU->Node->getTargetOpcode();
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2007-09-13 00:06:00 +00:00
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unsigned NumRes = TII->getNumDefs(Opc);
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2006-11-04 09:44:31 +00:00
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unsigned NumOps = CountOperands(SU->Node);
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for (unsigned j = 0; j != NumOps; ++j) {
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2006-12-01 21:52:58 +00:00
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if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1)
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2006-11-04 09:44:31 +00:00
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continue;
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SDNode *OpN = SU->Node->getOperand(j).Val;
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2007-09-25 01:54:36 +00:00
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SUnit *OpSU = SUnitMap[OpN][SU->InstanceNo];
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2006-11-04 09:44:31 +00:00
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if (OpSU && OperandSeen.count(OpSU) == 1) {
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// Ok, so SU is not the last use of OpSU, but SU is two-address so
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// it will clobber OpSU. Try to commute SU if no other source operands
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// are live below.
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bool DoCommute = true;
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for (unsigned k = 0; k < NumOps; ++k) {
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if (k != j) {
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OpN = SU->Node->getOperand(k).Val;
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2007-09-25 01:54:36 +00:00
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OpSU = SUnitMap[OpN][SU->InstanceNo];
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2006-11-04 09:44:31 +00:00
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if (OpSU && OperandSeen.count(OpSU) == 1) {
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DoCommute = false;
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break;
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}
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}
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2006-05-12 01:58:24 +00:00
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}
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2006-11-04 09:44:31 +00:00
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if (DoCommute)
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CommuteSet.insert(SU->Node);
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2006-05-12 01:58:24 +00:00
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}
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2006-11-04 09:44:31 +00:00
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// Only look at the first use&def node for now.
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break;
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2006-05-12 01:58:24 +00:00
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}
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}
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2006-08-17 00:09:56 +00:00
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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2007-09-19 01:38:40 +00:00
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if (!I->isCtrl)
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OperandSeen.insert(I->Dep);
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2006-05-12 01:58:24 +00:00
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}
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}
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}
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2006-05-11 23:55:42 +00:00
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//===----------------------------------------------------------------------===//
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// Bottom-Up Scheduling
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//===----------------------------------------------------------------------===//
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
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2007-08-20 19:28:38 +00:00
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/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
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2006-05-11 23:55:42 +00:00
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void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
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unsigned CurCycle) {
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// FIXME: the distance between two nodes is not always == the predecessor's
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// latency. For example, the reader can very well read the register written
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// by the predecessor later than the issue cycle. It also depends on the
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// interrupt model (drain vs. freeze).
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PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
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2007-09-28 19:24:24 +00:00
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--PredSU->NumSuccsLeft;
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2006-05-11 23:55:42 +00:00
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#ifndef NDEBUG
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2007-09-28 19:24:24 +00:00
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if (PredSU->NumSuccsLeft < 0) {
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2006-12-07 20:04:42 +00:00
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cerr << "*** List scheduling failed! ***\n";
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2006-05-11 23:55:42 +00:00
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PredSU->dump(&DAG);
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2006-12-07 20:04:42 +00:00
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cerr << " has been released too many times!\n";
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2006-05-11 23:55:42 +00:00
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assert(0);
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}
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#endif
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2007-09-28 19:24:24 +00:00
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if (PredSU->NumSuccsLeft == 0) {
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2006-05-11 23:55:42 +00:00
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// EntryToken has to go last! Special case it here.
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2007-09-26 21:36:17 +00:00
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if (!PredSU->Node || PredSU->Node->getOpcode() != ISD::EntryToken) {
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2006-05-11 23:55:42 +00:00
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PredSU->isAvailable = true;
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AvailableQueue->push(PredSU);
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}
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}
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}
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/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
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/// count of its predecessors. If a predecessor pending count is zero, add it to
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/// the Available queue.
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2006-05-30 18:05:39 +00:00
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void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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2006-12-07 20:04:42 +00:00
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DOUT << "*** Scheduling [" << CurCycle << "]: ";
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2006-05-11 23:55:42 +00:00
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DEBUG(SU->dump(&DAG));
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SU->Cycle = CurCycle;
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AvailableQueue->ScheduledNode(SU);
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// Bottom up: release predecessors
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2006-08-17 00:09:56 +00:00
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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2007-09-25 01:54:36 +00:00
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I != E; ++I) {
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2007-09-19 01:38:40 +00:00
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ReleasePred(I->Dep, I->isCtrl, CurCycle);
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2007-09-25 01:54:36 +00:00
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if (I->Cost < 0) {
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// This is a physical register dependency and it's impossible or
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// expensive to copy the register. Make sure nothing that can
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// clobber the register is scheduled between the predecessor and
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// this node.
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if (LiveRegs.insert(I->Reg)) {
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LiveRegDefs[I->Reg] = I->Dep;
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LiveRegCycles[I->Reg] = CurCycle;
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}
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}
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}
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// Release all the implicit physical register defs that are live.
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->Cost < 0) {
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if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
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LiveRegs.erase(I->Reg);
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assert(LiveRegDefs[I->Reg] == SU &&
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"Physical register dependency violated?");
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LiveRegDefs[I->Reg] = NULL;
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LiveRegCycles[I->Reg] = 0;
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}
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}
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}
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2006-05-11 23:55:42 +00:00
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SU->isScheduled = true;
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}
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2007-09-25 01:54:36 +00:00
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/// CapturePred - This does the opposite of ReleasePred. Since SU is being
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/// unscheduled, incrcease the succ left count of its predecessors. Remove
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/// them from AvailableQueue if necessary.
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void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) {
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PredSU->CycleBound = 0;
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for (SUnit::succ_iterator I = PredSU->Succs.begin(), E = PredSU->Succs.end();
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I != E; ++I) {
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if (I->Dep == SU)
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continue;
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PredSU->CycleBound = std::max(PredSU->CycleBound,
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I->Dep->Cycle + PredSU->Latency);
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}
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if (PredSU->isAvailable) {
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PredSU->isAvailable = false;
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if (!PredSU->isPending)
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AvailableQueue->remove(PredSU);
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}
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2007-09-28 19:24:24 +00:00
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++PredSU->NumSuccsLeft;
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2007-09-25 01:54:36 +00:00
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}
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/// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and
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/// its predecessor states to reflect the change.
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void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
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DOUT << "*** Unscheduling [" << SU->Cycle << "]: ";
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DEBUG(SU->dump(&DAG));
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AvailableQueue->UnscheduledNode(SU);
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
|
|
I != E; ++I) {
|
|
|
|
CapturePred(I->Dep, SU, I->isCtrl);
|
|
|
|
if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg]) {
|
|
|
|
LiveRegs.erase(I->Reg);
|
|
|
|
assert(LiveRegDefs[I->Reg] == I->Dep &&
|
|
|
|
"Physical register dependency violated?");
|
|
|
|
LiveRegDefs[I->Reg] = NULL;
|
|
|
|
LiveRegCycles[I->Reg] = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
|
|
I != E; ++I) {
|
|
|
|
if (I->Cost < 0) {
|
|
|
|
if (LiveRegs.insert(I->Reg)) {
|
|
|
|
assert(!LiveRegDefs[I->Reg] &&
|
|
|
|
"Physical register dependency violated?");
|
|
|
|
LiveRegDefs[I->Reg] = SU;
|
|
|
|
}
|
|
|
|
if (I->Dep->Cycle < LiveRegCycles[I->Reg])
|
|
|
|
LiveRegCycles[I->Reg] = I->Dep->Cycle;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
SU->Cycle = 0;
|
|
|
|
SU->isScheduled = false;
|
|
|
|
SU->isAvailable = true;
|
|
|
|
AvailableQueue->push(SU);
|
|
|
|
}
|
|
|
|
|
2007-09-27 00:25:29 +00:00
|
|
|
// FIXME: This is probably too slow!
|
|
|
|
static void isReachable(SUnit *SU, SUnit *TargetSU,
|
|
|
|
SmallPtrSet<SUnit*, 32> &Visited, bool &Reached) {
|
|
|
|
if (Reached) return;
|
|
|
|
if (SU == TargetSU) {
|
|
|
|
Reached = true;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (!Visited.insert(SU)) return;
|
|
|
|
|
|
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E;
|
|
|
|
++I)
|
|
|
|
isReachable(I->Dep, TargetSU, Visited, Reached);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool isReachable(SUnit *SU, SUnit *TargetSU) {
|
|
|
|
SmallPtrSet<SUnit*, 32> Visited;
|
|
|
|
bool Reached = false;
|
|
|
|
isReachable(SU, TargetSU, Visited, Reached);
|
|
|
|
return Reached;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// willCreateCycle - Returns true if adding an edge from SU to TargetSU will
|
|
|
|
/// create a cycle.
|
2007-09-27 07:09:03 +00:00
|
|
|
static bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
|
2007-09-27 00:25:29 +00:00
|
|
|
if (isReachable(TargetSU, SU))
|
|
|
|
return true;
|
|
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
|
|
I != E; ++I)
|
|
|
|
if (I->Cost < 0 && isReachable(TargetSU, I->Dep))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2007-09-26 21:36:17 +00:00
|
|
|
/// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
|
2007-09-25 01:54:36 +00:00
|
|
|
/// BTCycle in order to schedule a specific node. Returns the last unscheduled
|
|
|
|
/// SUnit. Also returns if a successor is unscheduled in the process.
|
2007-09-26 21:36:17 +00:00
|
|
|
void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, unsigned BtCycle,
|
|
|
|
unsigned &CurCycle) {
|
2007-09-25 01:54:36 +00:00
|
|
|
SUnit *OldSU = NULL;
|
2007-09-26 21:36:17 +00:00
|
|
|
while (CurCycle > BtCycle) {
|
2007-09-25 01:54:36 +00:00
|
|
|
OldSU = Sequence.back();
|
|
|
|
Sequence.pop_back();
|
|
|
|
if (SU->isSucc(OldSU))
|
2007-09-26 21:36:17 +00:00
|
|
|
// Don't try to remove SU from AvailableQueue.
|
|
|
|
SU->isAvailable = false;
|
2007-09-25 01:54:36 +00:00
|
|
|
UnscheduleNodeBottomUp(OldSU);
|
|
|
|
--CurCycle;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (SU->isSucc(OldSU)) {
|
|
|
|
assert(false && "Something is wrong!");
|
|
|
|
abort();
|
|
|
|
}
|
2007-09-27 07:09:03 +00:00
|
|
|
|
|
|
|
++NumBacktracks;
|
2007-09-25 01:54:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// isSafeToCopy - True if the SUnit for the given SDNode can safely cloned,
|
|
|
|
/// i.e. the node does not produce a flag, it does not read a flag and it does
|
|
|
|
/// not have an incoming chain.
|
|
|
|
static bool isSafeToCopy(SDNode *N) {
|
2007-09-26 21:36:17 +00:00
|
|
|
if (!N)
|
|
|
|
return true;
|
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i)
|
|
|
|
if (N->getValueType(i) == MVT::Flag)
|
|
|
|
return false;
|
|
|
|
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
|
|
|
|
const SDOperand &Op = N->getOperand(i);
|
|
|
|
MVT::ValueType VT = Op.Val->getValueType(Op.ResNo);
|
|
|
|
if (VT == MVT::Other || VT == MVT::Flag)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
|
|
|
|
/// successors to the newly created node.
|
|
|
|
SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
|
2007-09-26 21:36:17 +00:00
|
|
|
DOUT << "Duplicating SU # " << SU->NodeNum << "\n";
|
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
SUnit *NewSU = Clone(SU);
|
|
|
|
|
|
|
|
// New SUnit has the exact same predecessors.
|
|
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
|
|
I != E; ++I)
|
|
|
|
if (!I->isSpecial) {
|
|
|
|
NewSU->addPred(I->Dep, I->isCtrl, false, I->Reg, I->Cost);
|
|
|
|
NewSU->Depth = std::max(NewSU->Depth, I->Dep->Depth+1);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Only copy scheduled successors. Cut them from old node's successor
|
|
|
|
// list and move them over.
|
2007-09-27 07:29:27 +00:00
|
|
|
SmallVector<std::pair<SUnit*, bool>, 4> DelDeps;
|
2007-09-25 01:54:36 +00:00
|
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
|
|
I != E; ++I) {
|
|
|
|
if (I->isSpecial)
|
|
|
|
continue;
|
|
|
|
if (I->Dep->isScheduled) {
|
2007-09-27 07:29:27 +00:00
|
|
|
NewSU->Height = std::max(NewSU->Height, I->Dep->Height+1);
|
2007-09-25 01:54:36 +00:00
|
|
|
I->Dep->addPred(NewSU, I->isCtrl, false, I->Reg, I->Cost);
|
2007-09-27 07:29:27 +00:00
|
|
|
DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
|
2007-09-25 01:54:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
|
2007-09-27 07:29:27 +00:00
|
|
|
SUnit *Succ = DelDeps[i].first;
|
|
|
|
bool isCtrl = DelDeps[i].second;
|
2007-09-25 01:54:36 +00:00
|
|
|
Succ->removePred(SU, isCtrl, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
AvailableQueue->updateNode(SU);
|
|
|
|
AvailableQueue->addNode(NewSU);
|
|
|
|
|
2007-09-27 07:09:03 +00:00
|
|
|
++NumDups;
|
2007-09-25 01:54:36 +00:00
|
|
|
return NewSU;
|
|
|
|
}
|
|
|
|
|
2007-09-27 07:09:03 +00:00
|
|
|
/// InsertCCCopiesAndMoveSuccs - Insert expensive cross register class copies
|
|
|
|
/// and move all scheduled successors of the given SUnit to the last copy.
|
|
|
|
void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
|
|
|
|
const TargetRegisterClass *DestRC,
|
|
|
|
const TargetRegisterClass *SrcRC,
|
|
|
|
SmallVector<SUnit*, 2> &Copies) {
|
2007-09-26 21:36:17 +00:00
|
|
|
SUnit *CopyFromSU = NewSUnit(NULL);
|
|
|
|
CopyFromSU->CopySrcRC = SrcRC;
|
|
|
|
CopyFromSU->CopyDstRC = DestRC;
|
|
|
|
CopyFromSU->Depth = SU->Depth;
|
|
|
|
CopyFromSU->Height = SU->Height;
|
|
|
|
|
|
|
|
SUnit *CopyToSU = NewSUnit(NULL);
|
|
|
|
CopyToSU->CopySrcRC = DestRC;
|
|
|
|
CopyToSU->CopyDstRC = SrcRC;
|
|
|
|
|
|
|
|
// Only copy scheduled successors. Cut them from old node's successor
|
|
|
|
// list and move them over.
|
2007-09-27 07:29:27 +00:00
|
|
|
SmallVector<std::pair<SUnit*, bool>, 4> DelDeps;
|
2007-09-26 21:36:17 +00:00
|
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
|
|
I != E; ++I) {
|
|
|
|
if (I->isSpecial)
|
|
|
|
continue;
|
|
|
|
if (I->Dep->isScheduled) {
|
2007-09-27 07:29:27 +00:00
|
|
|
CopyToSU->Height = std::max(CopyToSU->Height, I->Dep->Height+1);
|
2007-09-26 21:36:17 +00:00
|
|
|
I->Dep->addPred(CopyToSU, I->isCtrl, false, I->Reg, I->Cost);
|
2007-09-27 07:29:27 +00:00
|
|
|
DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
|
2007-09-26 21:36:17 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
|
2007-09-27 07:29:27 +00:00
|
|
|
SUnit *Succ = DelDeps[i].first;
|
|
|
|
bool isCtrl = DelDeps[i].second;
|
2007-09-26 21:36:17 +00:00
|
|
|
Succ->removePred(SU, isCtrl, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
CopyFromSU->addPred(SU, false, false, Reg, -1);
|
|
|
|
CopyToSU->addPred(CopyFromSU, false, false, Reg, 1);
|
|
|
|
|
|
|
|
AvailableQueue->updateNode(SU);
|
|
|
|
AvailableQueue->addNode(CopyFromSU);
|
|
|
|
AvailableQueue->addNode(CopyToSU);
|
2007-09-27 07:09:03 +00:00
|
|
|
Copies.push_back(CopyFromSU);
|
|
|
|
Copies.push_back(CopyToSU);
|
2007-09-26 21:36:17 +00:00
|
|
|
|
2007-09-27 07:09:03 +00:00
|
|
|
++NumCCCopies;
|
2007-09-26 21:36:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// getPhysicalRegisterVT - Returns the ValueType of the physical register
|
|
|
|
/// definition of the specified node.
|
|
|
|
/// FIXME: Move to SelectionDAG?
|
|
|
|
static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg,
|
|
|
|
const TargetInstrInfo *TII) {
|
|
|
|
const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
|
|
|
|
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
|
|
|
|
unsigned NumRes = TID.numDefs;
|
|
|
|
for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef) {
|
|
|
|
if (Reg == *ImpDef)
|
|
|
|
break;
|
|
|
|
++NumRes;
|
|
|
|
}
|
|
|
|
return N->getValueType(NumRes);
|
|
|
|
}
|
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
/// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
|
|
|
|
/// scheduling of the given node to satisfy live physical register dependencies.
|
|
|
|
/// If the specific node is the last one that's available to schedule, do
|
|
|
|
/// whatever is necessary (i.e. backtracking or cloning) to make it possible.
|
2007-09-27 07:09:03 +00:00
|
|
|
bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
|
|
|
|
SmallVector<unsigned, 4> &LRegs){
|
2007-09-25 01:54:36 +00:00
|
|
|
if (LiveRegs.empty())
|
|
|
|
return false;
|
|
|
|
|
2007-09-27 18:46:06 +00:00
|
|
|
SmallSet<unsigned, 4> RegAdded;
|
2007-09-25 01:54:36 +00:00
|
|
|
// If this node would clobber any "live" register, then it's not ready.
|
|
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
|
|
I != E; ++I) {
|
|
|
|
if (I->Cost < 0) {
|
|
|
|
unsigned Reg = I->Reg;
|
2007-09-27 18:46:06 +00:00
|
|
|
if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
|
|
|
|
if (RegAdded.insert(Reg))
|
|
|
|
LRegs.push_back(Reg);
|
|
|
|
}
|
2007-09-25 01:54:36 +00:00
|
|
|
for (const unsigned *Alias = MRI->getAliasSet(Reg);
|
|
|
|
*Alias; ++Alias)
|
2007-09-27 18:46:06 +00:00
|
|
|
if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
|
|
|
|
if (RegAdded.insert(*Alias))
|
|
|
|
LRegs.push_back(*Alias);
|
|
|
|
}
|
2007-09-25 01:54:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) {
|
|
|
|
SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
|
2007-09-26 21:36:17 +00:00
|
|
|
if (!Node || !Node->isTargetOpcode())
|
2007-09-25 01:54:36 +00:00
|
|
|
continue;
|
|
|
|
const TargetInstrDescriptor &TID = TII->get(Node->getTargetOpcode());
|
|
|
|
if (!TID.ImplicitDefs)
|
|
|
|
continue;
|
|
|
|
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
|
2007-09-27 18:46:06 +00:00
|
|
|
if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
|
|
|
|
if (RegAdded.insert(*Reg))
|
|
|
|
LRegs.push_back(*Reg);
|
|
|
|
}
|
2007-09-25 01:54:36 +00:00
|
|
|
for (const unsigned *Alias = MRI->getAliasSet(*Reg);
|
|
|
|
*Alias; ++Alias)
|
2007-09-27 18:46:06 +00:00
|
|
|
if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
|
|
|
|
if (RegAdded.insert(*Alias))
|
|
|
|
LRegs.push_back(*Alias);
|
|
|
|
}
|
2007-09-25 01:54:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return !LRegs.empty();
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
2007-09-27 07:09:03 +00:00
|
|
|
|
2006-05-11 23:55:42 +00:00
|
|
|
/// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
|
|
|
|
/// schedulers.
|
|
|
|
void ScheduleDAGRRList::ListScheduleBottomUp() {
|
|
|
|
unsigned CurCycle = 0;
|
|
|
|
// Add root to Available queue.
|
2007-09-25 01:54:36 +00:00
|
|
|
SUnit *RootSU = SUnitMap[DAG.getRoot().Val].front();
|
|
|
|
RootSU->isAvailable = true;
|
|
|
|
AvailableQueue->push(RootSU);
|
2006-05-11 23:55:42 +00:00
|
|
|
|
|
|
|
// While Available queue is not empty, grab the node with the highest
|
2007-08-20 19:28:38 +00:00
|
|
|
// priority. If it is not ready put it back. Schedule the node.
|
2007-09-25 01:54:36 +00:00
|
|
|
SmallVector<SUnit*, 4> NotReady;
|
2006-05-11 23:55:42 +00:00
|
|
|
while (!AvailableQueue->empty()) {
|
2007-09-27 07:09:03 +00:00
|
|
|
bool Delayed = false;
|
|
|
|
DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;
|
2007-09-25 01:54:36 +00:00
|
|
|
SUnit *CurSU = AvailableQueue->pop();
|
|
|
|
while (CurSU) {
|
2007-09-27 07:09:03 +00:00
|
|
|
if (CurSU->CycleBound <= CurCycle) {
|
|
|
|
SmallVector<unsigned, 4> LRegs;
|
|
|
|
if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
|
2007-09-25 01:54:36 +00:00
|
|
|
break;
|
2007-09-27 07:09:03 +00:00
|
|
|
Delayed = true;
|
|
|
|
LRegsMap.insert(std::make_pair(CurSU, LRegs));
|
2007-09-25 01:54:36 +00:00
|
|
|
}
|
2007-09-27 07:09:03 +00:00
|
|
|
|
|
|
|
CurSU->isPending = true; // This SU is not in AvailableQueue right now.
|
|
|
|
NotReady.push_back(CurSU);
|
2007-09-25 01:54:36 +00:00
|
|
|
CurSU = AvailableQueue->pop();
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
2007-09-27 07:09:03 +00:00
|
|
|
|
|
|
|
// All candidates are delayed due to live physical reg dependencies.
|
|
|
|
// Try backtracking, code duplication, or inserting cross class copies
|
|
|
|
// to resolve it.
|
|
|
|
if (Delayed && !CurSU) {
|
|
|
|
for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
|
|
|
|
SUnit *TrySU = NotReady[i];
|
|
|
|
SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
|
|
|
|
|
|
|
|
// Try unscheduling up to the point where it's safe to schedule
|
|
|
|
// this node.
|
|
|
|
unsigned LiveCycle = CurCycle;
|
|
|
|
for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) {
|
|
|
|
unsigned Reg = LRegs[j];
|
|
|
|
unsigned LCycle = LiveRegCycles[Reg];
|
|
|
|
LiveCycle = std::min(LiveCycle, LCycle);
|
|
|
|
}
|
|
|
|
SUnit *OldSU = Sequence[LiveCycle];
|
|
|
|
if (!WillCreateCycle(TrySU, OldSU)) {
|
|
|
|
BacktrackBottomUp(TrySU, LiveCycle, CurCycle);
|
|
|
|
// Force the current node to be scheduled before the node that
|
|
|
|
// requires the physical reg dep.
|
|
|
|
if (OldSU->isAvailable) {
|
|
|
|
OldSU->isAvailable = false;
|
|
|
|
AvailableQueue->remove(OldSU);
|
|
|
|
}
|
|
|
|
TrySU->addPred(OldSU, true, true);
|
|
|
|
// If one or more successors has been unscheduled, then the current
|
|
|
|
// node is no longer avaialable. Schedule a successor that's now
|
|
|
|
// available instead.
|
|
|
|
if (!TrySU->isAvailable)
|
|
|
|
CurSU = AvailableQueue->pop();
|
|
|
|
else {
|
|
|
|
CurSU = TrySU;
|
|
|
|
TrySU->isPending = false;
|
|
|
|
NotReady.erase(NotReady.begin()+i);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!CurSU) {
|
|
|
|
// Can't backtrace. Try duplicating the nodes that produces these
|
|
|
|
// "expensive to copy" values to break the dependency. In case even
|
|
|
|
// that doesn't work, insert cross class copies.
|
|
|
|
SUnit *TrySU = NotReady[0];
|
|
|
|
SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
|
|
|
|
assert(LRegs.size() == 1 && "Can't handle this yet!");
|
|
|
|
unsigned Reg = LRegs[0];
|
|
|
|
SUnit *LRDef = LiveRegDefs[Reg];
|
|
|
|
SUnit *NewDef;
|
|
|
|
if (isSafeToCopy(LRDef->Node))
|
|
|
|
NewDef = CopyAndMoveSuccessors(LRDef);
|
|
|
|
else {
|
|
|
|
// Issue expensive cross register class copies.
|
|
|
|
MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
|
|
|
|
const TargetRegisterClass *RC =
|
|
|
|
MRI->getPhysicalRegisterRegClass(VT, Reg);
|
|
|
|
const TargetRegisterClass *DestRC = MRI->getCrossCopyRegClass(RC);
|
|
|
|
if (!DestRC) {
|
|
|
|
assert(false && "Don't know how to copy this physical register!");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
SmallVector<SUnit*, 2> Copies;
|
|
|
|
InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
|
|
|
|
DOUT << "Adding an edge from SU # " << TrySU->NodeNum
|
|
|
|
<< " to SU #" << Copies.front()->NodeNum << "\n";
|
|
|
|
TrySU->addPred(Copies.front(), true, true);
|
|
|
|
NewDef = Copies.back();
|
|
|
|
}
|
|
|
|
|
|
|
|
DOUT << "Adding an edge from SU # " << NewDef->NodeNum
|
|
|
|
<< " to SU #" << TrySU->NodeNum << "\n";
|
|
|
|
LiveRegDefs[Reg] = NewDef;
|
|
|
|
NewDef->addPred(TrySU, true, true);
|
|
|
|
TrySU->isAvailable = false;
|
|
|
|
CurSU = NewDef;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!CurSU) {
|
|
|
|
assert(false && "Unable to resolve live physical register dependencies!");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-05-11 23:55:42 +00:00
|
|
|
// Add the nodes that aren't ready back onto the available list.
|
2007-09-25 01:54:36 +00:00
|
|
|
for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
|
|
|
|
NotReady[i]->isPending = false;
|
2007-09-27 07:09:03 +00:00
|
|
|
// May no longer be available due to backtracking.
|
2007-09-25 01:54:36 +00:00
|
|
|
if (NotReady[i]->isAvailable)
|
|
|
|
AvailableQueue->push(NotReady[i]);
|
|
|
|
}
|
2006-05-11 23:55:42 +00:00
|
|
|
NotReady.clear();
|
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
if (!CurSU)
|
|
|
|
Sequence.push_back(0);
|
|
|
|
else {
|
|
|
|
ScheduleNodeBottomUp(CurSU, CurCycle);
|
|
|
|
Sequence.push_back(CurSU);
|
|
|
|
}
|
|
|
|
++CurCycle;
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Add entry node last
|
|
|
|
if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
|
2007-09-25 01:54:36 +00:00
|
|
|
SUnit *Entry = SUnitMap[DAG.getEntryNode().Val].front();
|
2006-05-11 23:55:42 +00:00
|
|
|
Sequence.push_back(Entry);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Reverse the order if it is bottom up.
|
|
|
|
std::reverse(Sequence.begin(), Sequence.end());
|
|
|
|
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
// Verify that all SUnits were scheduled.
|
|
|
|
bool AnyNotSched = false;
|
|
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
2007-09-28 19:24:24 +00:00
|
|
|
if (SUnits[i].NumSuccsLeft != 0) {
|
2006-05-11 23:55:42 +00:00
|
|
|
if (!AnyNotSched)
|
2006-12-07 20:04:42 +00:00
|
|
|
cerr << "*** List scheduling failed! ***\n";
|
2006-05-11 23:55:42 +00:00
|
|
|
SUnits[i].dump(&DAG);
|
2006-12-07 20:04:42 +00:00
|
|
|
cerr << "has not been scheduled!\n";
|
2006-05-11 23:55:42 +00:00
|
|
|
AnyNotSched = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
assert(!AnyNotSched);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Top-Down Scheduling
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
|
2007-08-20 19:28:38 +00:00
|
|
|
/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
|
2006-05-11 23:55:42 +00:00
|
|
|
void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
|
|
|
|
unsigned CurCycle) {
|
|
|
|
// FIXME: the distance between two nodes is not always == the predecessor's
|
|
|
|
// latency. For example, the reader can very well read the register written
|
|
|
|
// by the predecessor later than the issue cycle. It also depends on the
|
|
|
|
// interrupt model (drain vs. freeze).
|
|
|
|
SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurCycle + SuccSU->Latency);
|
|
|
|
|
2007-09-28 19:24:24 +00:00
|
|
|
--SuccSU->NumPredsLeft;
|
2006-05-11 23:55:42 +00:00
|
|
|
|
|
|
|
#ifndef NDEBUG
|
2007-09-28 19:24:24 +00:00
|
|
|
if (SuccSU->NumPredsLeft < 0) {
|
2006-12-07 20:04:42 +00:00
|
|
|
cerr << "*** List scheduling failed! ***\n";
|
2006-05-11 23:55:42 +00:00
|
|
|
SuccSU->dump(&DAG);
|
2006-12-07 20:04:42 +00:00
|
|
|
cerr << " has been released too many times!\n";
|
2006-05-11 23:55:42 +00:00
|
|
|
assert(0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2007-09-28 19:24:24 +00:00
|
|
|
if (SuccSU->NumPredsLeft == 0) {
|
2006-05-11 23:55:42 +00:00
|
|
|
SuccSU->isAvailable = true;
|
|
|
|
AvailableQueue->push(SuccSU);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
|
|
|
|
/// count of its successors. If a successor pending count is zero, add it to
|
|
|
|
/// the Available queue.
|
2006-05-30 18:05:39 +00:00
|
|
|
void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
|
2006-12-07 20:04:42 +00:00
|
|
|
DOUT << "*** Scheduling [" << CurCycle << "]: ";
|
2006-05-11 23:55:42 +00:00
|
|
|
DEBUG(SU->dump(&DAG));
|
|
|
|
SU->Cycle = CurCycle;
|
|
|
|
|
|
|
|
AvailableQueue->ScheduledNode(SU);
|
|
|
|
|
|
|
|
// Top down: release successors
|
2006-08-17 00:09:56 +00:00
|
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
|
|
I != E; ++I)
|
2007-09-19 01:38:40 +00:00
|
|
|
ReleaseSucc(I->Dep, I->isCtrl, CurCycle);
|
2006-05-11 23:55:42 +00:00
|
|
|
SU->isScheduled = true;
|
|
|
|
}
|
|
|
|
|
2007-08-20 19:28:38 +00:00
|
|
|
/// ListScheduleTopDown - The main loop of list scheduling for top-down
|
|
|
|
/// schedulers.
|
2006-05-11 23:55:42 +00:00
|
|
|
void ScheduleDAGRRList::ListScheduleTopDown() {
|
|
|
|
unsigned CurCycle = 0;
|
2007-09-25 01:54:36 +00:00
|
|
|
SUnit *Entry = SUnitMap[DAG.getEntryNode().Val].front();
|
2006-05-11 23:55:42 +00:00
|
|
|
|
|
|
|
// All leaves to Available queue.
|
|
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
|
|
|
// It is available if it has no predecessors.
|
|
|
|
if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
|
|
|
|
AvailableQueue->push(&SUnits[i]);
|
|
|
|
SUnits[i].isAvailable = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Emit the entry node first.
|
|
|
|
ScheduleNodeTopDown(Entry, CurCycle);
|
2007-09-25 01:54:36 +00:00
|
|
|
Sequence.push_back(Entry);
|
|
|
|
++CurCycle;
|
2006-05-11 23:55:42 +00:00
|
|
|
|
|
|
|
// While Available queue is not empty, grab the node with the highest
|
2007-08-20 19:28:38 +00:00
|
|
|
// priority. If it is not ready put it back. Schedule the node.
|
2006-05-11 23:55:42 +00:00
|
|
|
std::vector<SUnit*> NotReady;
|
|
|
|
while (!AvailableQueue->empty()) {
|
2007-09-25 01:54:36 +00:00
|
|
|
SUnit *CurSU = AvailableQueue->pop();
|
|
|
|
while (CurSU && CurSU->CycleBound > CurCycle) {
|
|
|
|
NotReady.push_back(CurSU);
|
|
|
|
CurSU = AvailableQueue->pop();
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Add the nodes that aren't ready back onto the available list.
|
|
|
|
AvailableQueue->push_all(NotReady);
|
|
|
|
NotReady.clear();
|
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
if (!CurSU)
|
|
|
|
Sequence.push_back(0);
|
|
|
|
else {
|
|
|
|
ScheduleNodeTopDown(CurSU, CurCycle);
|
|
|
|
Sequence.push_back(CurSU);
|
|
|
|
}
|
2006-05-30 18:05:39 +00:00
|
|
|
CurCycle++;
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
// Verify that all SUnits were scheduled.
|
|
|
|
bool AnyNotSched = false;
|
|
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
|
|
|
if (!SUnits[i].isScheduled) {
|
|
|
|
if (!AnyNotSched)
|
2006-12-07 20:04:42 +00:00
|
|
|
cerr << "*** List scheduling failed! ***\n";
|
2006-05-11 23:55:42 +00:00
|
|
|
SUnits[i].dump(&DAG);
|
2006-12-07 20:04:42 +00:00
|
|
|
cerr << "has not been scheduled!\n";
|
2006-05-11 23:55:42 +00:00
|
|
|
AnyNotSched = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
assert(!AnyNotSched);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// RegReductionPriorityQueue Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
|
|
|
|
// to reduce register pressure.
|
|
|
|
//
|
|
|
|
namespace {
|
|
|
|
template<class SF>
|
|
|
|
class RegReductionPriorityQueue;
|
|
|
|
|
|
|
|
/// Sorting functions for the Available queue.
|
|
|
|
struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
|
|
|
|
RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
|
|
|
|
bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
|
|
|
|
bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
|
|
|
|
|
|
|
|
bool operator()(const SUnit* left, const SUnit* right) const;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
|
|
|
|
RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
|
|
|
|
td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
|
|
|
|
td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
|
|
|
|
|
|
|
|
bool operator()(const SUnit* left, const SUnit* right) const;
|
|
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
|
2007-01-08 23:50:38 +00:00
|
|
|
static inline bool isCopyFromLiveIn(const SUnit *SU) {
|
|
|
|
SDNode *N = SU->Node;
|
2007-09-26 21:36:17 +00:00
|
|
|
return N && N->getOpcode() == ISD::CopyFromReg &&
|
2007-01-08 23:50:38 +00:00
|
|
|
N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag;
|
|
|
|
}
|
|
|
|
|
2006-05-11 23:55:42 +00:00
|
|
|
namespace {
|
|
|
|
template<class SF>
|
2006-06-28 23:17:24 +00:00
|
|
|
class VISIBILITY_HIDDEN RegReductionPriorityQueue
|
|
|
|
: public SchedulingPriorityQueue {
|
2006-05-11 23:55:42 +00:00
|
|
|
std::priority_queue<SUnit*, std::vector<SUnit*>, SF> Queue;
|
|
|
|
|
|
|
|
public:
|
|
|
|
RegReductionPriorityQueue() :
|
|
|
|
Queue(SF(this)) {}
|
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
virtual void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap,
|
2006-11-04 09:44:31 +00:00
|
|
|
std::vector<SUnit> &sunits) {}
|
2007-09-25 01:54:36 +00:00
|
|
|
|
|
|
|
virtual void addNode(const SUnit *SU) {}
|
|
|
|
|
|
|
|
virtual void updateNode(const SUnit *SU) {}
|
|
|
|
|
2006-05-11 23:55:42 +00:00
|
|
|
virtual void releaseState() {}
|
|
|
|
|
2007-01-08 23:55:53 +00:00
|
|
|
virtual unsigned getNodePriority(const SUnit *SU) const {
|
2006-05-11 23:55:42 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
unsigned size() const { return Queue.size(); }
|
|
|
|
|
2006-05-11 23:55:42 +00:00
|
|
|
bool empty() const { return Queue.empty(); }
|
|
|
|
|
|
|
|
void push(SUnit *U) {
|
|
|
|
Queue.push(U);
|
|
|
|
}
|
|
|
|
void push_all(const std::vector<SUnit *> &Nodes) {
|
|
|
|
for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
|
|
|
|
Queue.push(Nodes[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
SUnit *pop() {
|
2006-05-30 18:05:39 +00:00
|
|
|
if (empty()) return NULL;
|
2006-05-11 23:55:42 +00:00
|
|
|
SUnit *V = Queue.top();
|
|
|
|
Queue.pop();
|
|
|
|
return V;
|
|
|
|
}
|
2006-11-04 09:44:31 +00:00
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
/// remove - This is a really inefficient way to remove a node from a
|
|
|
|
/// priority queue. We should roll our own heap to make this better or
|
|
|
|
/// something.
|
|
|
|
void remove(SUnit *SU) {
|
|
|
|
std::vector<SUnit*> Temp;
|
|
|
|
|
|
|
|
assert(!Queue.empty() && "Not in queue!");
|
|
|
|
while (Queue.top() != SU) {
|
|
|
|
Temp.push_back(Queue.top());
|
|
|
|
Queue.pop();
|
|
|
|
assert(!Queue.empty() && "Not in queue!");
|
|
|
|
}
|
|
|
|
|
|
|
|
// Remove the node from the PQ.
|
|
|
|
Queue.pop();
|
|
|
|
|
|
|
|
// Add all the other nodes back.
|
|
|
|
for (unsigned i = 0, e = Temp.size(); i != e; ++i)
|
|
|
|
Queue.push(Temp[i]);
|
2006-11-04 09:44:31 +00:00
|
|
|
}
|
2006-05-11 23:55:42 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
template<class SF>
|
2006-06-28 23:17:24 +00:00
|
|
|
class VISIBILITY_HIDDEN BURegReductionPriorityQueue
|
|
|
|
: public RegReductionPriorityQueue<SF> {
|
2007-09-25 01:54:36 +00:00
|
|
|
// SUnitMap SDNode to SUnit mapping (n -> n).
|
|
|
|
DenseMap<SDNode*, std::vector<SUnit*> > *SUnitMap;
|
2006-11-04 09:44:31 +00:00
|
|
|
|
2006-05-11 23:55:42 +00:00
|
|
|
// SUnits - The SUnits for the current graph.
|
|
|
|
const std::vector<SUnit> *SUnits;
|
|
|
|
|
|
|
|
// SethiUllmanNumbers - The SethiUllman number for each node.
|
2007-01-08 23:50:38 +00:00
|
|
|
std::vector<unsigned> SethiUllmanNumbers;
|
2006-05-11 23:55:42 +00:00
|
|
|
|
2006-11-04 09:44:31 +00:00
|
|
|
const TargetInstrInfo *TII;
|
2006-05-11 23:55:42 +00:00
|
|
|
public:
|
2007-08-20 19:28:38 +00:00
|
|
|
explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii)
|
2006-11-04 09:44:31 +00:00
|
|
|
: TII(tii) {}
|
2006-05-11 23:55:42 +00:00
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap,
|
2006-11-04 09:44:31 +00:00
|
|
|
std::vector<SUnit> &sunits) {
|
|
|
|
SUnitMap = &sumap;
|
2006-05-11 23:55:42 +00:00
|
|
|
SUnits = &sunits;
|
|
|
|
// Add pseudo dependency edges for two-address nodes.
|
2006-05-12 01:58:24 +00:00
|
|
|
AddPseudoTwoAddrDeps();
|
2006-05-11 23:55:42 +00:00
|
|
|
// Calculate node priorities.
|
2007-01-08 23:55:53 +00:00
|
|
|
CalculateSethiUllmanNumbers();
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
void addNode(const SUnit *SU) {
|
|
|
|
SethiUllmanNumbers.resize(SUnits->size(), 0);
|
|
|
|
CalcNodeSethiUllmanNumber(SU);
|
|
|
|
}
|
|
|
|
|
|
|
|
void updateNode(const SUnit *SU) {
|
|
|
|
SethiUllmanNumbers[SU->NodeNum] = 0;
|
|
|
|
CalcNodeSethiUllmanNumber(SU);
|
|
|
|
}
|
|
|
|
|
2006-05-11 23:55:42 +00:00
|
|
|
void releaseState() {
|
|
|
|
SUnits = 0;
|
|
|
|
SethiUllmanNumbers.clear();
|
|
|
|
}
|
|
|
|
|
2007-01-08 23:55:53 +00:00
|
|
|
unsigned getNodePriority(const SUnit *SU) const {
|
2007-01-08 23:50:38 +00:00
|
|
|
assert(SU->NodeNum < SethiUllmanNumbers.size());
|
2007-09-26 21:36:17 +00:00
|
|
|
unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
|
2007-01-08 23:50:38 +00:00
|
|
|
if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU))
|
|
|
|
// CopyFromReg should be close to its def because it restricts
|
|
|
|
// allocation choices. But if it is a livein then perhaps we want it
|
|
|
|
// closer to its uses so it can be coalesced.
|
|
|
|
return 0xffff;
|
|
|
|
else if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
|
|
|
|
// CopyToReg should be close to its uses to facilitate coalescing and
|
|
|
|
// avoid spilling.
|
|
|
|
return 0;
|
|
|
|
else if (SU->NumSuccs == 0)
|
|
|
|
// If SU does not have a use, i.e. it doesn't produce a value that would
|
|
|
|
// be consumed (e.g. store), then it terminates a chain of computation.
|
|
|
|
// Give it a large SethiUllman number so it will be scheduled right
|
|
|
|
// before its predecessors that it doesn't lengthen their live ranges.
|
|
|
|
return 0xffff;
|
|
|
|
else if (SU->NumPreds == 0)
|
|
|
|
// If SU does not have a def, schedule it close to its uses because it
|
|
|
|
// does not lengthen any live ranges.
|
|
|
|
return 0;
|
|
|
|
else
|
|
|
|
return SethiUllmanNumbers[SU->NodeNum];
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
2006-11-04 09:44:31 +00:00
|
|
|
bool canClobber(SUnit *SU, SUnit *Op);
|
2006-05-11 23:55:42 +00:00
|
|
|
void AddPseudoTwoAddrDeps();
|
2007-01-08 23:55:53 +00:00
|
|
|
void CalculateSethiUllmanNumbers();
|
|
|
|
unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
|
2006-05-11 23:55:42 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
template<class SF>
|
2007-08-20 19:28:38 +00:00
|
|
|
class VISIBILITY_HIDDEN TDRegReductionPriorityQueue
|
|
|
|
: public RegReductionPriorityQueue<SF> {
|
2007-09-25 01:54:36 +00:00
|
|
|
// SUnitMap SDNode to SUnit mapping (n -> n).
|
|
|
|
DenseMap<SDNode*, std::vector<SUnit*> > *SUnitMap;
|
2006-11-04 09:44:31 +00:00
|
|
|
|
2006-05-11 23:55:42 +00:00
|
|
|
// SUnits - The SUnits for the current graph.
|
|
|
|
const std::vector<SUnit> *SUnits;
|
|
|
|
|
|
|
|
// SethiUllmanNumbers - The SethiUllman number for each node.
|
2007-01-08 23:50:38 +00:00
|
|
|
std::vector<unsigned> SethiUllmanNumbers;
|
2006-05-11 23:55:42 +00:00
|
|
|
|
|
|
|
public:
|
|
|
|
TDRegReductionPriorityQueue() {}
|
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap,
|
2006-11-04 09:44:31 +00:00
|
|
|
std::vector<SUnit> &sunits) {
|
|
|
|
SUnitMap = &sumap;
|
2006-05-11 23:55:42 +00:00
|
|
|
SUnits = &sunits;
|
|
|
|
// Calculate node priorities.
|
2007-01-08 23:55:53 +00:00
|
|
|
CalculateSethiUllmanNumbers();
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
2007-09-25 01:54:36 +00:00
|
|
|
void addNode(const SUnit *SU) {
|
|
|
|
SethiUllmanNumbers.resize(SUnits->size(), 0);
|
|
|
|
CalcNodeSethiUllmanNumber(SU);
|
|
|
|
}
|
|
|
|
|
|
|
|
void updateNode(const SUnit *SU) {
|
|
|
|
SethiUllmanNumbers[SU->NodeNum] = 0;
|
|
|
|
CalcNodeSethiUllmanNumber(SU);
|
|
|
|
}
|
|
|
|
|
2006-05-11 23:55:42 +00:00
|
|
|
void releaseState() {
|
|
|
|
SUnits = 0;
|
|
|
|
SethiUllmanNumbers.clear();
|
|
|
|
}
|
|
|
|
|
2007-01-08 23:55:53 +00:00
|
|
|
unsigned getNodePriority(const SUnit *SU) const {
|
2007-01-08 23:50:38 +00:00
|
|
|
assert(SU->NodeNum < SethiUllmanNumbers.size());
|
|
|
|
return SethiUllmanNumbers[SU->NodeNum];
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
2007-01-08 23:55:53 +00:00
|
|
|
void CalculateSethiUllmanNumbers();
|
|
|
|
unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
|
2006-05-11 23:55:42 +00:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2007-03-14 22:43:40 +00:00
|
|
|
/// closestSucc - Returns the scheduled cycle of the successor which is
|
|
|
|
/// closet to the current cycle.
|
2007-03-13 23:25:11 +00:00
|
|
|
static unsigned closestSucc(const SUnit *SU) {
|
|
|
|
unsigned MaxCycle = 0;
|
|
|
|
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
2007-03-14 22:43:40 +00:00
|
|
|
I != E; ++I) {
|
2007-09-19 01:38:40 +00:00
|
|
|
unsigned Cycle = I->Dep->Cycle;
|
2007-03-14 22:43:40 +00:00
|
|
|
// If there are bunch of CopyToRegs stacked up, they should be considered
|
|
|
|
// to be at the same position.
|
2007-09-26 21:36:17 +00:00
|
|
|
if (I->Dep->Node && I->Dep->Node->getOpcode() == ISD::CopyToReg)
|
2007-09-19 01:38:40 +00:00
|
|
|
Cycle = closestSucc(I->Dep)+1;
|
2007-03-14 22:43:40 +00:00
|
|
|
if (Cycle > MaxCycle)
|
|
|
|
MaxCycle = Cycle;
|
|
|
|
}
|
2007-03-13 23:25:11 +00:00
|
|
|
return MaxCycle;
|
|
|
|
}
|
|
|
|
|
2007-03-14 22:43:40 +00:00
|
|
|
/// calcMaxScratches - Returns an cost estimate of the worse case requirement
|
|
|
|
/// for scratch registers. Live-in operands and live-out results don't count
|
|
|
|
/// since they are "fixed".
|
|
|
|
static unsigned calcMaxScratches(const SUnit *SU) {
|
|
|
|
unsigned Scratches = 0;
|
|
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
|
|
I != E; ++I) {
|
2007-09-19 01:38:40 +00:00
|
|
|
if (I->isCtrl) continue; // ignore chain preds
|
2007-09-26 21:36:17 +00:00
|
|
|
if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyFromReg)
|
2007-03-14 22:43:40 +00:00
|
|
|
Scratches++;
|
|
|
|
}
|
|
|
|
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
|
|
I != E; ++I) {
|
2007-09-19 01:38:40 +00:00
|
|
|
if (I->isCtrl) continue; // ignore chain succs
|
2007-09-26 21:36:17 +00:00
|
|
|
if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyToReg)
|
2007-03-14 22:43:40 +00:00
|
|
|
Scratches += 10;
|
|
|
|
}
|
|
|
|
return Scratches;
|
|
|
|
}
|
|
|
|
|
2006-05-11 23:55:42 +00:00
|
|
|
// Bottom up
|
|
|
|
bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
|
2007-06-29 03:42:23 +00:00
|
|
|
// There used to be a special tie breaker here that looked for
|
2007-06-29 02:48:09 +00:00
|
|
|
// two-address instructions and preferred the instruction with a
|
|
|
|
// def&use operand. The special case triggered diagnostics when
|
|
|
|
// _GLIBCXX_DEBUG was enabled because it broke the strict weak
|
|
|
|
// ordering that priority_queue requires. It didn't help much anyway
|
|
|
|
// because AddPseudoTwoAddrDeps already covers many of the cases
|
|
|
|
// where it would have applied. In addition, it's counter-intuitive
|
|
|
|
// that a tie breaker would be the first thing attempted. There's a
|
|
|
|
// "real" tie breaker below that is the operation of last resort.
|
|
|
|
// The fact that the "special tie breaker" would trigger when there
|
|
|
|
// wasn't otherwise a tie is what broke the strict weak ordering
|
|
|
|
// constraint.
|
2006-05-13 08:22:24 +00:00
|
|
|
|
2007-01-08 23:55:53 +00:00
|
|
|
unsigned LPriority = SPQ->getNodePriority(left);
|
|
|
|
unsigned RPriority = SPQ->getNodePriority(right);
|
2007-01-08 23:50:38 +00:00
|
|
|
if (LPriority > RPriority)
|
2006-05-11 23:55:42 +00:00
|
|
|
return true;
|
2007-03-13 23:25:11 +00:00
|
|
|
else if (LPriority == RPriority) {
|
2007-04-26 19:40:56 +00:00
|
|
|
// Try schedule def + use closer when Sethi-Ullman numbers are the same.
|
2007-03-13 23:25:11 +00:00
|
|
|
// e.g.
|
|
|
|
// t1 = op t2, c1
|
|
|
|
// t3 = op t4, c2
|
|
|
|
//
|
|
|
|
// and the following instructions are both ready.
|
|
|
|
// t2 = op c3
|
|
|
|
// t4 = op c4
|
|
|
|
//
|
|
|
|
// Then schedule t2 = op first.
|
|
|
|
// i.e.
|
|
|
|
// t4 = op c4
|
|
|
|
// t2 = op c3
|
|
|
|
// t1 = op t2, c1
|
|
|
|
// t3 = op t4, c2
|
|
|
|
//
|
|
|
|
// This creates more short live intervals.
|
|
|
|
unsigned LDist = closestSucc(left);
|
|
|
|
unsigned RDist = closestSucc(right);
|
|
|
|
if (LDist < RDist)
|
2006-05-11 23:55:42 +00:00
|
|
|
return true;
|
2007-03-14 22:43:40 +00:00
|
|
|
else if (LDist == RDist) {
|
|
|
|
// Intuitively, it's good to push down instructions whose results are
|
|
|
|
// liveout so their long live ranges won't conflict with other values
|
|
|
|
// which are needed inside the BB. Further prioritize liveout instructions
|
|
|
|
// by the number of operands which are calculated within the BB.
|
|
|
|
unsigned LScratch = calcMaxScratches(left);
|
|
|
|
unsigned RScratch = calcMaxScratches(right);
|
|
|
|
if (LScratch > RScratch)
|
2006-05-11 23:55:42 +00:00
|
|
|
return true;
|
2007-03-14 22:43:40 +00:00
|
|
|
else if (LScratch == RScratch)
|
|
|
|
if (left->Height > right->Height)
|
2006-05-13 08:22:24 +00:00
|
|
|
return true;
|
2007-03-14 22:43:40 +00:00
|
|
|
else if (left->Height == right->Height)
|
|
|
|
if (left->Depth < right->Depth)
|
2007-03-13 23:25:11 +00:00
|
|
|
return true;
|
2007-03-14 22:43:40 +00:00
|
|
|
else if (left->Depth == right->Depth)
|
|
|
|
if (left->CycleBound > right->CycleBound)
|
|
|
|
return true;
|
|
|
|
}
|
2007-03-13 23:25:11 +00:00
|
|
|
}
|
2006-05-11 23:55:42 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-11-04 09:44:31 +00:00
|
|
|
template<class SF>
|
|
|
|
bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
|
|
|
|
if (SU->isTwoAddress) {
|
|
|
|
unsigned Opc = SU->Node->getTargetOpcode();
|
2007-09-13 00:06:00 +00:00
|
|
|
unsigned NumRes = TII->getNumDefs(Opc);
|
2006-11-04 09:44:31 +00:00
|
|
|
unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
|
|
|
|
for (unsigned i = 0; i != NumOps; ++i) {
|
2006-12-01 21:52:58 +00:00
|
|
|
if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) {
|
2006-11-04 09:44:31 +00:00
|
|
|
SDNode *DU = SU->Node->getOperand(i).Val;
|
2007-09-25 01:54:36 +00:00
|
|
|
if (Op == (*SUnitMap)[DU][SU->InstanceNo])
|
2006-11-04 09:44:31 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-11-04 09:44:31 +00:00
|
|
|
|
2006-05-11 23:55:42 +00:00
|
|
|
/// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
|
|
|
|
/// it as a def&use operand. Add a pseudo control edge from it to the other
|
|
|
|
/// node (if it won't create a cycle) so the two-address one will be scheduled
|
|
|
|
/// first (lower in the schedule).
|
|
|
|
template<class SF>
|
|
|
|
void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
|
2006-11-04 09:44:31 +00:00
|
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
|
|
|
|
SUnit *SU = (SUnit *)&((*SUnits)[i]);
|
|
|
|
if (!SU->isTwoAddress)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
SDNode *Node = SU->Node;
|
2007-09-26 21:36:17 +00:00
|
|
|
if (!Node || !Node->isTargetOpcode())
|
2006-11-04 09:44:31 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
unsigned Opc = Node->getTargetOpcode();
|
2007-09-13 00:06:00 +00:00
|
|
|
unsigned NumRes = TII->getNumDefs(Opc);
|
2006-11-04 09:44:31 +00:00
|
|
|
unsigned NumOps = ScheduleDAG::CountOperands(Node);
|
|
|
|
for (unsigned j = 0; j != NumOps; ++j) {
|
2006-12-01 21:52:58 +00:00
|
|
|
if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) {
|
2006-11-04 09:44:31 +00:00
|
|
|
SDNode *DU = SU->Node->getOperand(j).Val;
|
2007-09-25 01:54:36 +00:00
|
|
|
SUnit *DUSU = (*SUnitMap)[DU][SU->InstanceNo];
|
2006-11-06 21:33:46 +00:00
|
|
|
if (!DUSU) continue;
|
2006-11-04 09:44:31 +00:00
|
|
|
for (SUnit::succ_iterator I = DUSU->Succs.begin(),E = DUSU->Succs.end();
|
|
|
|
I != E; ++I) {
|
2007-09-19 01:38:40 +00:00
|
|
|
if (I->isCtrl) continue;
|
|
|
|
SUnit *SuccSU = I->Dep;
|
2007-09-25 01:54:36 +00:00
|
|
|
// Don't constraint nodes with implicit defs. It can create cycles
|
|
|
|
// plus it may increase register pressures.
|
|
|
|
if (SuccSU == SU || SuccSU->hasImplicitDefs)
|
|
|
|
continue;
|
|
|
|
// Be conservative. Ignore if nodes aren't at the same depth.
|
|
|
|
if (SuccSU->Depth != SU->Depth)
|
|
|
|
continue;
|
|
|
|
if ((!canClobber(SuccSU, DUSU) ||
|
|
|
|
(!SU->isCommutable && SuccSU->isCommutable)) &&
|
|
|
|
!isReachable(SuccSU, SU)) {
|
|
|
|
DOUT << "Adding an edge from SU # " << SU->NodeNum
|
|
|
|
<< " to SU #" << SuccSU->NodeNum << "\n";
|
|
|
|
SU->addPred(SuccSU, true, true);
|
2006-11-04 09:44:31 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
2007-01-08 23:55:53 +00:00
|
|
|
/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
|
2006-05-11 23:55:42 +00:00
|
|
|
/// Smaller number is the higher priority.
|
|
|
|
template<class SF>
|
2007-02-01 04:55:59 +00:00
|
|
|
unsigned BURegReductionPriorityQueue<SF>::
|
|
|
|
CalcNodeSethiUllmanNumber(const SUnit *SU) {
|
2007-01-08 23:50:38 +00:00
|
|
|
unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
|
2006-05-11 23:55:42 +00:00
|
|
|
if (SethiUllmanNumber != 0)
|
|
|
|
return SethiUllmanNumber;
|
|
|
|
|
2007-01-08 23:50:38 +00:00
|
|
|
unsigned Extra = 0;
|
|
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
|
|
I != E; ++I) {
|
2007-09-19 01:38:40 +00:00
|
|
|
if (I->isCtrl) continue; // ignore chain preds
|
|
|
|
SUnit *PredSU = I->Dep;
|
2007-01-08 23:55:53 +00:00
|
|
|
unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
|
2007-01-08 23:50:38 +00:00
|
|
|
if (PredSethiUllman > SethiUllmanNumber) {
|
|
|
|
SethiUllmanNumber = PredSethiUllman;
|
|
|
|
Extra = 0;
|
2007-09-19 01:38:40 +00:00
|
|
|
} else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
|
2007-09-25 01:54:36 +00:00
|
|
|
++Extra;
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
2007-01-08 23:50:38 +00:00
|
|
|
|
|
|
|
SethiUllmanNumber += Extra;
|
|
|
|
|
|
|
|
if (SethiUllmanNumber == 0)
|
|
|
|
SethiUllmanNumber = 1;
|
2006-05-11 23:55:42 +00:00
|
|
|
|
|
|
|
return SethiUllmanNumber;
|
|
|
|
}
|
|
|
|
|
2007-01-08 23:55:53 +00:00
|
|
|
/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
|
|
|
|
/// scheduling units.
|
2006-05-11 23:55:42 +00:00
|
|
|
template<class SF>
|
2007-01-08 23:55:53 +00:00
|
|
|
void BURegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() {
|
2006-05-11 23:55:42 +00:00
|
|
|
SethiUllmanNumbers.assign(SUnits->size(), 0);
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
|
2007-01-08 23:55:53 +00:00
|
|
|
CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned SumOfUnscheduledPredsOfSuccs(const SUnit *SU) {
|
|
|
|
unsigned Sum = 0;
|
2006-08-17 00:09:56 +00:00
|
|
|
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
|
|
I != E; ++I) {
|
2007-09-19 01:38:40 +00:00
|
|
|
SUnit *SuccSU = I->Dep;
|
2006-08-17 00:09:56 +00:00
|
|
|
for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(),
|
|
|
|
EE = SuccSU->Preds.end(); II != EE; ++II) {
|
2007-09-19 01:38:40 +00:00
|
|
|
SUnit *PredSU = II->Dep;
|
2006-05-11 23:55:42 +00:00
|
|
|
if (!PredSU->isScheduled)
|
2007-09-25 01:54:36 +00:00
|
|
|
++Sum;
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return Sum;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Top down
|
|
|
|
bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
|
2007-01-08 23:55:53 +00:00
|
|
|
unsigned LPriority = SPQ->getNodePriority(left);
|
|
|
|
unsigned RPriority = SPQ->getNodePriority(right);
|
2007-09-26 21:36:17 +00:00
|
|
|
bool LIsTarget = left->Node && left->Node->isTargetOpcode();
|
|
|
|
bool RIsTarget = right->Node && right->Node->isTargetOpcode();
|
2006-05-11 23:55:42 +00:00
|
|
|
bool LIsFloater = LIsTarget && left->NumPreds == 0;
|
|
|
|
bool RIsFloater = RIsTarget && right->NumPreds == 0;
|
|
|
|
unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left) == 1) ? 2 : 0;
|
|
|
|
unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right) == 1) ? 2 : 0;
|
|
|
|
|
|
|
|
if (left->NumSuccs == 0 && right->NumSuccs != 0)
|
|
|
|
return false;
|
|
|
|
else if (left->NumSuccs != 0 && right->NumSuccs == 0)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Special tie breaker: if two nodes share a operand, the one that use it
|
|
|
|
// as a def&use operand is preferred.
|
|
|
|
if (LIsTarget && RIsTarget) {
|
|
|
|
if (left->isTwoAddress && !right->isTwoAddress) {
|
|
|
|
SDNode *DUNode = left->Node->getOperand(0).Val;
|
|
|
|
if (DUNode->isOperand(right->Node))
|
|
|
|
RBonus += 2;
|
|
|
|
}
|
|
|
|
if (!left->isTwoAddress && right->isTwoAddress) {
|
|
|
|
SDNode *DUNode = right->Node->getOperand(0).Val;
|
|
|
|
if (DUNode->isOperand(left->Node))
|
|
|
|
LBonus += 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (LIsFloater)
|
|
|
|
LBonus -= 2;
|
|
|
|
if (RIsFloater)
|
|
|
|
RBonus -= 2;
|
|
|
|
if (left->NumSuccs == 1)
|
|
|
|
LBonus += 2;
|
|
|
|
if (right->NumSuccs == 1)
|
|
|
|
RBonus += 2;
|
|
|
|
|
|
|
|
if (LPriority+LBonus < RPriority+RBonus)
|
|
|
|
return true;
|
|
|
|
else if (LPriority == RPriority)
|
|
|
|
if (left->Depth < right->Depth)
|
|
|
|
return true;
|
|
|
|
else if (left->Depth == right->Depth)
|
|
|
|
if (left->NumSuccsLeft > right->NumSuccsLeft)
|
|
|
|
return true;
|
|
|
|
else if (left->NumSuccsLeft == right->NumSuccsLeft)
|
|
|
|
if (left->CycleBound > right->CycleBound)
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2007-01-08 23:55:53 +00:00
|
|
|
/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
|
2006-05-11 23:55:42 +00:00
|
|
|
/// Smaller number is the higher priority.
|
|
|
|
template<class SF>
|
2007-02-01 04:55:59 +00:00
|
|
|
unsigned TDRegReductionPriorityQueue<SF>::
|
|
|
|
CalcNodeSethiUllmanNumber(const SUnit *SU) {
|
2007-01-08 23:50:38 +00:00
|
|
|
unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
|
2006-05-11 23:55:42 +00:00
|
|
|
if (SethiUllmanNumber != 0)
|
|
|
|
return SethiUllmanNumber;
|
|
|
|
|
2007-09-26 21:36:17 +00:00
|
|
|
unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
|
2006-05-11 23:55:42 +00:00
|
|
|
if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
|
2007-01-08 23:50:38 +00:00
|
|
|
SethiUllmanNumber = 0xffff;
|
2006-05-11 23:55:42 +00:00
|
|
|
else if (SU->NumSuccsLeft == 0)
|
|
|
|
// If SU does not have a use, i.e. it doesn't produce a value that would
|
|
|
|
// be consumed (e.g. store), then it terminates a chain of computation.
|
2007-02-01 04:55:59 +00:00
|
|
|
// Give it a small SethiUllman number so it will be scheduled right before
|
|
|
|
// its predecessors that it doesn't lengthen their live ranges.
|
2007-01-08 23:50:38 +00:00
|
|
|
SethiUllmanNumber = 0;
|
2006-05-11 23:55:42 +00:00
|
|
|
else if (SU->NumPredsLeft == 0 &&
|
|
|
|
(Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
|
2007-01-08 23:50:38 +00:00
|
|
|
SethiUllmanNumber = 0xffff;
|
2006-05-11 23:55:42 +00:00
|
|
|
else {
|
|
|
|
int Extra = 0;
|
2006-08-17 00:09:56 +00:00
|
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
|
|
I != E; ++I) {
|
2007-09-19 01:38:40 +00:00
|
|
|
if (I->isCtrl) continue; // ignore chain preds
|
|
|
|
SUnit *PredSU = I->Dep;
|
2007-01-08 23:55:53 +00:00
|
|
|
unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
|
2006-05-11 23:55:42 +00:00
|
|
|
if (PredSethiUllman > SethiUllmanNumber) {
|
|
|
|
SethiUllmanNumber = PredSethiUllman;
|
|
|
|
Extra = 0;
|
2007-09-19 01:38:40 +00:00
|
|
|
} else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
|
2007-09-25 01:54:36 +00:00
|
|
|
++Extra;
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SethiUllmanNumber += Extra;
|
|
|
|
}
|
|
|
|
|
|
|
|
return SethiUllmanNumber;
|
|
|
|
}
|
|
|
|
|
2007-01-08 23:55:53 +00:00
|
|
|
/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
|
|
|
|
/// scheduling units.
|
2006-05-11 23:55:42 +00:00
|
|
|
template<class SF>
|
2007-01-08 23:55:53 +00:00
|
|
|
void TDRegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() {
|
2006-05-11 23:55:42 +00:00
|
|
|
SethiUllmanNumbers.assign(SUnits->size(), 0);
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
|
2007-01-08 23:55:53 +00:00
|
|
|
CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Public Constructor Functions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2006-08-01 18:29:48 +00:00
|
|
|
llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
|
|
|
|
SelectionDAG *DAG,
|
2006-05-11 23:55:42 +00:00
|
|
|
MachineBasicBlock *BB) {
|
2006-11-04 09:44:31 +00:00
|
|
|
const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
|
2006-08-01 14:21:23 +00:00
|
|
|
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true,
|
2006-11-04 09:44:31 +00:00
|
|
|
new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII));
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|
2006-08-01 18:29:48 +00:00
|
|
|
llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
|
|
|
|
SelectionDAG *DAG,
|
2006-05-11 23:55:42 +00:00
|
|
|
MachineBasicBlock *BB) {
|
2006-08-01 14:21:23 +00:00
|
|
|
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false,
|
2007-02-01 04:55:59 +00:00
|
|
|
new TDRegReductionPriorityQueue<td_ls_rr_sort>());
|
2006-05-11 23:55:42 +00:00
|
|
|
}
|
|
|
|
|