2002-11-22 22:42:50 +00:00
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//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
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2003-10-20 19:43:21 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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2002-10-25 22:55:53 +00:00
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//
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2003-01-14 22:00:31 +00:00
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// This file contains the X86 implementation of the TargetInstrInfo class.
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2002-10-25 22:55:53 +00:00
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//
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//===----------------------------------------------------------------------===//
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2002-10-29 21:05:24 +00:00
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#include "X86InstrInfo.h"
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2002-12-03 05:42:53 +00:00
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#include "X86.h"
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2005-01-02 02:37:07 +00:00
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#include "X86InstrBuilder.h"
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2003-05-24 00:09:50 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2003-08-03 21:55:55 +00:00
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#include "X86GenInstrInfo.inc"
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2003-11-11 22:41:34 +00:00
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using namespace llvm;
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2002-10-29 21:05:24 +00:00
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X86InstrInfo::X86InstrInfo()
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2004-02-29 06:31:44 +00:00
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: TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
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2002-10-25 22:55:53 +00:00
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}
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2003-12-28 17:35:08 +00:00
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bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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A big X86 instruction rename. The instructions are renamed to make
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:
ADD8rr -> add, 8-bit register, 8-bit register
IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate
IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate
MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11995 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-29 08:50:03 +00:00
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if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
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oc == X86::FpMOV) {
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2003-12-28 17:35:08 +00:00
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid register-register move instruction");
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2004-02-13 21:01:20 +00:00
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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2003-12-28 17:35:08 +00:00
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return true;
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}
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return false;
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}
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2004-07-31 09:38:47 +00:00
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2005-01-02 02:37:07 +00:00
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// three-address instruction on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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///
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MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
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// All instructions input are two-addr instructions. Get the known operands.
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Src = MI->getOperand(1).getReg();
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2005-01-02 04:18:17 +00:00
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// FIXME: None of these instructions are promotable to LEAs without
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// additional information. In particular, LEA doesn't set the flags that
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// add and inc do. :(
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return 0;
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2005-01-02 02:37:07 +00:00
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// FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
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// we have subtarget support, enable the 16-bit LEA generation here.
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bool DisableLEA16 = true;
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switch (MI->getOpcode()) {
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case X86::INC32r:
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assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
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return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
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case X86::INC16r:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
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return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
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case X86::DEC32r:
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assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
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return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
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case X86::DEC16r:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
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return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
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case X86::ADD32rr:
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
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MI->getOperand(2).getReg());
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case X86::ADD16rr:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
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MI->getOperand(2).getReg());
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case X86::ADD32ri:
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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if (MI->getOperand(2).isImmediate())
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return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
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MI->getOperand(2).getImmedValue());
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return 0;
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case X86::ADD16ri:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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if (MI->getOperand(2).isImmediate())
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return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
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MI->getOperand(2).getImmedValue());
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break;
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case X86::SHL16ri:
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if (DisableLEA16) return 0;
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case X86::SHL32ri:
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assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
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"Unknown shl instruction!");
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unsigned ShAmt = MI->getOperand(2).getImmedValue();
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if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
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X86AddressMode AM;
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AM.Scale = 1 << ShAmt;
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AM.IndexReg = Src;
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unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
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return addFullAddress(BuildMI(Opc, 5, Dest), AM);
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}
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break;
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}
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return 0;
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}
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2004-07-31 09:38:47 +00:00
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void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
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MachineBasicBlock& TMBB) const {
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BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
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}
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MachineBasicBlock::iterator
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X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
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unsigned Opcode = MI->getOpcode();
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assert(isBranch(Opcode) && "MachineInstr must be a branch");
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unsigned ROpcode;
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switch (Opcode) {
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2004-08-01 19:31:30 +00:00
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default: assert(0 && "Cannot reverse unconditional branches!");
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2004-07-31 09:53:31 +00:00
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case X86::JB: ROpcode = X86::JAE; break;
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2004-07-31 10:05:44 +00:00
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case X86::JAE: ROpcode = X86::JB; break;
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2004-07-31 09:53:31 +00:00
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case X86::JE: ROpcode = X86::JNE; break;
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2004-07-31 10:05:44 +00:00
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case X86::JNE: ROpcode = X86::JE; break;
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case X86::JBE: ROpcode = X86::JA; break;
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2004-07-31 09:53:31 +00:00
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case X86::JA: ROpcode = X86::JBE; break;
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case X86::JS: ROpcode = X86::JNS; break;
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2004-07-31 10:05:44 +00:00
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case X86::JNS: ROpcode = X86::JS; break;
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2005-01-02 02:37:07 +00:00
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case X86::JP: ROpcode = X86::JNP; break;
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case X86::JNP: ROpcode = X86::JP; break;
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2004-07-31 09:53:31 +00:00
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case X86::JL: ROpcode = X86::JGE; break;
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2004-07-31 10:05:44 +00:00
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case X86::JGE: ROpcode = X86::JL; break;
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case X86::JLE: ROpcode = X86::JG; break;
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2004-07-31 09:53:31 +00:00
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case X86::JG: ROpcode = X86::JLE; break;
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2004-07-31 09:38:47 +00:00
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}
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MachineBasicBlock* MBB = MI->getParent();
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MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
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2004-07-31 09:44:32 +00:00
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return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);
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2004-07-31 09:38:47 +00:00
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}
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2005-01-02 02:37:07 +00:00
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