2004-07-23 17:56:30 +00:00
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//===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
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2003-11-20 03:32:25 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2004-07-19 02:13:59 +00:00
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// This file implements the LiveInterval analysis pass. Given some numbering of
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// each the machine instructions (in this implemention depth-first order) an
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// interval [i, j) is said to be a live interval for register v if there is no
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// instruction with number j' > j such that v is live at j' abd there is no
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// instruction with number i' < i such that v is live at i'. In this
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// implementation intervals can have holes, i.e. an interval might look like
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// [1,20), [50,65), [1000,1001).
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2003-11-20 03:32:25 +00:00
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//
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//===----------------------------------------------------------------------===//
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2004-07-23 17:56:30 +00:00
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#ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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2003-11-20 03:32:25 +00:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2005-09-21 04:18:25 +00:00
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#include "llvm/CodeGen/LiveInterval.h"
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2007-02-15 05:59:24 +00:00
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#include "llvm/ADT/BitVector.h"
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2007-04-17 20:32:26 +00:00
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#include "llvm/ADT/DenseMap.h"
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2007-02-01 05:32:05 +00:00
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#include "llvm/ADT/IndexedMap.h"
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2007-08-13 23:45:17 +00:00
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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2003-11-20 03:32:25 +00:00
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namespace llvm {
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2004-08-04 09:46:26 +00:00
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class LiveVariables;
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class MRegisterInfo;
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Allow the live interval analysis pass to be a bit more aggressive about
numbering values in live ranges for physical registers.
The alpha backend currently generates code that looks like this:
vreg = preg
...
preg = vreg
use preg
...
preg = vreg
use preg
etc. Because vreg contains the value of preg coming in, each of the
copies back into preg contain that initial value as well.
In the case of the Alpha, this allows this testcase:
void "foo"(int %blah) {
store int 5, int *%MyVar
store int 12, int* %MyVar2
ret void
}
to compile to:
foo:
ldgp $29, 0($27)
ldiq $0,5
stl $0,MyVar
ldiq $0,12
stl $0,MyVar2
ret $31,($26),1
instead of:
foo:
ldgp $29, 0($27)
bis $29,$29,$0
ldiq $1,5
bis $0,$0,$29
stl $1,MyVar
ldiq $1,12
bis $0,$0,$29
stl $1,MyVar2
ret $31,($26),1
This does not seem to have any noticable effect on X86 code.
This fixes PR535.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20536 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-09 23:05:19 +00:00
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class TargetInstrInfo;
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2007-04-17 20:32:26 +00:00
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class TargetRegisterClass;
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2004-08-04 09:46:26 +00:00
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class VirtRegMap;
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class LiveIntervals : public MachineFunctionPass {
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MachineFunction* mf_;
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const TargetMachine* tm_;
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const MRegisterInfo* mri_;
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Allow the live interval analysis pass to be a bit more aggressive about
numbering values in live ranges for physical registers.
The alpha backend currently generates code that looks like this:
vreg = preg
...
preg = vreg
use preg
...
preg = vreg
use preg
etc. Because vreg contains the value of preg coming in, each of the
copies back into preg contain that initial value as well.
In the case of the Alpha, this allows this testcase:
void "foo"(int %blah) {
store int 5, int *%MyVar
store int 12, int* %MyVar2
ret void
}
to compile to:
foo:
ldgp $29, 0($27)
ldiq $0,5
stl $0,MyVar
ldiq $0,12
stl $0,MyVar2
ret $31,($26),1
instead of:
foo:
ldgp $29, 0($27)
bis $29,$29,$0
ldiq $1,5
bis $0,$0,$29
stl $1,MyVar
ldiq $1,12
bis $0,$0,$29
stl $1,MyVar2
ret $31,($26),1
This does not seem to have any noticable effect on X86 code.
This fixes PR535.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20536 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-09 23:05:19 +00:00
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const TargetInstrInfo* tii_;
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2004-08-04 09:46:26 +00:00
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LiveVariables* lv_;
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2007-08-13 23:45:17 +00:00
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/// MBB2IdxMap - The indexes of the first and last instructions in the
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/// specified basic block.
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std::vector<std::pair<unsigned, unsigned> > MBB2IdxMap;
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2007-06-08 17:18:56 +00:00
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2004-08-04 09:46:26 +00:00
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typedef std::map<MachineInstr*, unsigned> Mi2IndexMap;
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Mi2IndexMap mi2iMap_;
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typedef std::vector<MachineInstr*> Index2MiMap;
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Index2MiMap i2miMap_;
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typedef std::map<unsigned, LiveInterval> Reg2IntervalMap;
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Reg2IntervalMap r2iMap_;
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2007-02-15 05:59:24 +00:00
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BitVector allocatableRegs_;
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2007-03-01 02:03:03 +00:00
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2007-08-13 23:45:17 +00:00
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std::vector<MachineInstr*> ClonedMIs;
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2004-08-04 09:46:26 +00:00
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public:
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2007-05-06 13:37:16 +00:00
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static char ID; // Pass identification, replacement for typeid
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2007-05-01 21:15:47 +00:00
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LiveIntervals() : MachineFunctionPass((intptr_t)&ID) {}
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2006-08-24 22:43:55 +00:00
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struct InstrSlots {
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2004-08-04 09:46:26 +00:00
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enum {
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LOAD = 0,
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USE = 1,
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DEF = 2,
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STORE = 3,
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2006-02-22 16:23:43 +00:00
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NUM = 4
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2004-08-04 09:46:26 +00:00
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};
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2003-11-20 03:32:25 +00:00
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};
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2004-08-04 09:46:26 +00:00
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static unsigned getBaseIndex(unsigned index) {
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return index - (index % InstrSlots::NUM);
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}
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static unsigned getBoundaryIndex(unsigned index) {
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return getBaseIndex(index + InstrSlots::NUM - 1);
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}
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static unsigned getLoadIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::LOAD;
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}
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static unsigned getUseIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::USE;
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}
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static unsigned getDefIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::DEF;
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}
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static unsigned getStoreIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::STORE;
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}
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typedef Reg2IntervalMap::iterator iterator;
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2004-09-30 15:59:17 +00:00
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typedef Reg2IntervalMap::const_iterator const_iterator;
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const_iterator begin() const { return r2iMap_.begin(); }
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const_iterator end() const { return r2iMap_.end(); }
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2004-08-04 09:46:26 +00:00
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iterator begin() { return r2iMap_.begin(); }
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iterator end() { return r2iMap_.end(); }
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unsigned getNumIntervals() const { return r2iMap_.size(); }
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LiveInterval &getInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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assert(I != r2iMap_.end() && "Interval does not exist for register");
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return I->second;
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}
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const LiveInterval &getInterval(unsigned reg) const {
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Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
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assert(I != r2iMap_.end() && "Interval does not exist for register");
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return I->second;
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}
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2007-02-19 21:49:54 +00:00
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bool hasInterval(unsigned reg) const {
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2007-03-01 02:03:03 +00:00
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return r2iMap_.count(reg);
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2007-02-19 21:49:54 +00:00
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}
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2006-09-15 03:57:23 +00:00
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/// getMBBStartIdx - Return the base index of the first instruction in the
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/// specified MachineBasicBlock.
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unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
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return getMBBStartIdx(MBB->getNumber());
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}
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unsigned getMBBStartIdx(unsigned MBBNo) const {
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assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
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2007-08-13 23:45:17 +00:00
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return MBB2IdxMap[MBBNo].first;
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}
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/// getMBBEndIdx - Return the store index of the last instruction in the
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/// specified MachineBasicBlock.
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unsigned getMBBEndIdx(MachineBasicBlock *MBB) const {
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return getMBBEndIdx(MBB->getNumber());
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}
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unsigned getMBBEndIdx(unsigned MBBNo) const {
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assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
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return MBB2IdxMap[MBBNo].second;
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2006-09-15 03:57:23 +00:00
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}
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2004-08-04 09:46:26 +00:00
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/// getInstructionIndex - returns the base index of instr
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unsigned getInstructionIndex(MachineInstr* instr) const {
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Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
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assert(it != mi2iMap_.end() && "Invalid instruction!");
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return it->second;
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}
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/// getInstructionFromIndex - given an index in any slot of an
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/// instruction return a pointer the instruction
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MachineInstr* getInstructionFromIndex(unsigned index) const {
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index /= InstrSlots::NUM; // convert index to vector index
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assert(index < i2miMap_.size() &&
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"index does not correspond to an instruction");
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return i2miMap_[index];
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}
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2007-06-08 17:18:56 +00:00
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// Interval creation
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LiveInterval &getOrCreateInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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if (I == r2iMap_.end())
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I = r2iMap_.insert(I, std::make_pair(reg, createInterval(reg)));
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return I->second;
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}
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2004-08-04 09:46:26 +00:00
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2006-11-16 02:41:50 +00:00
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/// CreateNewLiveInterval - Create a new live interval with the given live
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/// ranges. The new live interval will have an infinite spill weight.
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LiveInterval &CreateNewLiveInterval(const LiveInterval *LI,
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const std::vector<LiveRange> &LRs);
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2007-06-08 17:18:56 +00:00
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std::vector<LiveInterval*> addIntervalsForSpills(const LiveInterval& i,
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2007-08-13 23:45:17 +00:00
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VirtRegMap& vrm, unsigned reg);
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2004-08-04 09:46:26 +00:00
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2007-06-08 17:18:56 +00:00
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// Interval removal
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2004-08-04 09:46:26 +00:00
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2007-06-08 17:18:56 +00:00
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void removeInterval(unsigned Reg) {
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r2iMap_.erase(Reg);
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2006-12-17 05:15:13 +00:00
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}
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2004-09-30 15:59:17 +00:00
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2007-02-22 23:03:39 +00:00
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/// isRemoved - returns true if the specified machine instr has been
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/// removed.
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bool isRemoved(MachineInstr* instr) const {
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2007-02-22 23:52:23 +00:00
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return !mi2iMap_.count(instr);
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2007-02-22 23:03:39 +00:00
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}
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2006-08-24 22:43:55 +00:00
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/// RemoveMachineInstrFromMaps - This marks the specified machine instr as
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/// deleted.
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void RemoveMachineInstrFromMaps(MachineInstr *MI) {
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// remove index -> MachineInstr and
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// MachineInstr -> index mappings
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Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
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if (mi2i != mi2iMap_.end()) {
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i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
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mi2iMap_.erase(mi2i);
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}
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}
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2007-06-08 17:18:56 +00:00
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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/// print - Implement the dump method.
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virtual void print(std::ostream &O, const Module* = 0) const;
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void print(std::ostream *O, const Module* M = 0) const {
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if (O) print(*O, M);
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}
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private:
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2006-09-15 03:57:23 +00:00
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/// computeIntervals - Compute live intervals.
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2006-09-14 06:42:17 +00:00
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void computeIntervals();
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2006-09-02 05:26:01 +00:00
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2004-08-04 09:46:26 +00:00
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/// handleRegisterDef - update intervals for a register def
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/// (calls handlePhysicalRegisterDef and
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/// handleVirtualRegisterDef)
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2006-09-03 08:07:11 +00:00
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void handleRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI, unsigned MIIdx,
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2006-01-29 07:59:37 +00:00
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unsigned reg);
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2004-08-04 09:46:26 +00:00
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/// handleVirtualRegisterDef - update intervals for a virtual
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/// register def
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2006-09-03 08:07:11 +00:00
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void handleVirtualRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI,
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unsigned MIIdx,
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2004-08-04 09:46:26 +00:00
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LiveInterval& interval);
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Allow the live interval analysis pass to be a bit more aggressive about
numbering values in live ranges for physical registers.
The alpha backend currently generates code that looks like this:
vreg = preg
...
preg = vreg
use preg
...
preg = vreg
use preg
etc. Because vreg contains the value of preg coming in, each of the
copies back into preg contain that initial value as well.
In the case of the Alpha, this allows this testcase:
void "foo"(int %blah) {
store int 5, int *%MyVar
store int 12, int* %MyVar2
ret void
}
to compile to:
foo:
ldgp $29, 0($27)
ldiq $0,5
stl $0,MyVar
ldiq $0,12
stl $0,MyVar2
ret $31,($26),1
instead of:
foo:
ldgp $29, 0($27)
bis $29,$29,$0
ldiq $1,5
bis $0,$0,$29
stl $1,MyVar
ldiq $1,12
bis $0,$0,$29
stl $1,MyVar2
ret $31,($26),1
This does not seem to have any noticable effect on X86 code.
This fixes PR535.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20536 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-09 23:05:19 +00:00
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/// handlePhysicalRegisterDef - update intervals for a physical register
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2006-08-24 22:43:55 +00:00
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/// def.
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2004-08-04 09:46:26 +00:00
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void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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2006-09-03 08:07:11 +00:00
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unsigned MIIdx,
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2006-08-31 05:54:43 +00:00
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LiveInterval &interval,
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unsigned SrcReg);
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2004-08-04 09:46:26 +00:00
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2007-02-19 21:49:54 +00:00
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/// handleLiveInRegister - Create interval for a livein register.
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2007-02-21 22:41:17 +00:00
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void handleLiveInRegister(MachineBasicBlock* mbb,
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unsigned MIIdx,
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2007-04-25 07:30:23 +00:00
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LiveInterval &interval, bool isAlias = false);
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2007-02-19 21:49:54 +00:00
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2007-08-13 23:45:17 +00:00
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/// isReMaterializable - Returns true if the definition MI of the specified
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/// val# of the specified interval is re-materializable.
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bool isReMaterializable(const LiveInterval &li, unsigned ValNum,
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MachineInstr *MI);
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/// tryFoldMemoryOperand - Attempts to fold a spill / restore from slot
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/// to reg into ith operand of specified MI. If it is successul, MI is
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/// updated with the newly created MI and returns true.
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bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm, unsigned index,
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unsigned i, int slot, unsigned reg);
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2004-08-04 09:46:26 +00:00
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static LiveInterval createInterval(unsigned Reg);
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void printRegName(unsigned reg) const;
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};
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2003-11-20 03:32:25 +00:00
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} // End llvm namespace
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#endif
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