2005-01-07 07:46:03 +00:00
|
|
|
//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
|
2005-04-21 20:39:54 +00:00
|
|
|
//
|
2005-01-07 07:46:03 +00:00
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 19:59:42 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2005-04-21 20:39:54 +00:00
|
|
|
//
|
2005-01-07 07:46:03 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file implements the SelectionDAGISel class, which is used as the common
|
|
|
|
// base class for SelectionDAG-based instruction selectors.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
|
|
|
|
#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
|
|
|
|
|
2008-08-23 02:25:05 +00:00
|
|
|
#include "llvm/BasicBlock.h"
|
2005-01-07 07:46:03 +00:00
|
|
|
#include "llvm/Pass.h"
|
2006-03-27 01:32:24 +00:00
|
|
|
#include "llvm/Constant.h"
|
2006-08-07 22:16:08 +00:00
|
|
|
#include "llvm/CodeGen/SelectionDAG.h"
|
2009-07-31 18:16:33 +00:00
|
|
|
#include "llvm/CodeGen/MachineFunctionPass.h"
|
2005-01-07 07:46:03 +00:00
|
|
|
|
|
|
|
namespace llvm {
|
2008-09-03 23:12:08 +00:00
|
|
|
class FastISel;
|
2009-11-23 18:04:58 +00:00
|
|
|
class SelectionDAGBuilder;
|
2008-07-27 21:46:04 +00:00
|
|
|
class SDValue;
|
2007-12-31 04:13:23 +00:00
|
|
|
class MachineRegisterInfo;
|
2005-01-07 07:46:03 +00:00
|
|
|
class MachineBasicBlock;
|
|
|
|
class MachineFunction;
|
|
|
|
class MachineInstr;
|
2008-09-23 21:53:34 +00:00
|
|
|
class MachineModuleInfo;
|
2009-01-13 00:35:13 +00:00
|
|
|
class DwarfWriter;
|
2005-01-07 07:46:03 +00:00
|
|
|
class TargetLowering;
|
2008-10-14 23:54:11 +00:00
|
|
|
class TargetInstrInfo;
|
2005-01-07 07:46:03 +00:00
|
|
|
class FunctionLoweringInfo;
|
2009-01-15 22:18:12 +00:00
|
|
|
class ScheduleHazardRecognizer;
|
2008-08-17 18:44:35 +00:00
|
|
|
class GCFunctionInfo;
|
2009-02-11 04:27:20 +00:00
|
|
|
class ScheduleDAGSDNodes;
|
2007-03-07 16:25:09 +00:00
|
|
|
|
2005-01-07 07:46:03 +00:00
|
|
|
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
|
|
|
|
/// pattern-matching instruction selectors.
|
2009-07-31 18:16:33 +00:00
|
|
|
class SelectionDAGISel : public MachineFunctionPass {
|
2005-01-07 07:46:03 +00:00
|
|
|
public:
|
2009-01-15 19:20:50 +00:00
|
|
|
const TargetMachine &TM;
|
2005-01-07 07:46:03 +00:00
|
|
|
TargetLowering &TLI;
|
2008-08-27 23:52:12 +00:00
|
|
|
FunctionLoweringInfo *FuncInfo;
|
2009-01-15 19:20:50 +00:00
|
|
|
MachineFunction *MF;
|
|
|
|
MachineRegisterInfo *RegInfo;
|
2005-01-07 07:46:03 +00:00
|
|
|
SelectionDAG *CurDAG;
|
2009-11-23 18:04:58 +00:00
|
|
|
SelectionDAGBuilder *SDB;
|
2005-01-07 07:46:03 +00:00
|
|
|
MachineBasicBlock *BB;
|
2007-08-27 16:26:13 +00:00
|
|
|
AliasAnalysis *AA;
|
2008-08-17 18:44:35 +00:00
|
|
|
GCFunctionInfo *GFI;
|
2009-04-29 23:29:43 +00:00
|
|
|
CodeGenOpt::Level OptLevel;
|
2007-05-03 01:11:54 +00:00
|
|
|
static char ID;
|
2005-01-07 07:46:03 +00:00
|
|
|
|
2009-04-29 23:29:43 +00:00
|
|
|
explicit SelectionDAGISel(TargetMachine &tm,
|
|
|
|
CodeGenOpt::Level OL = CodeGenOpt::Default);
|
2008-08-27 23:52:12 +00:00
|
|
|
virtual ~SelectionDAGISel();
|
2006-08-01 19:14:14 +00:00
|
|
|
|
|
|
|
TargetLowering &getTargetLowering() { return TLI; }
|
2005-01-07 07:46:03 +00:00
|
|
|
|
2005-08-17 06:46:50 +00:00
|
|
|
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
|
2005-01-07 07:46:03 +00:00
|
|
|
|
2009-07-31 18:16:33 +00:00
|
|
|
virtual bool runOnMachineFunction(MachineFunction &MF);
|
2005-01-07 07:46:03 +00:00
|
|
|
|
2009-08-10 22:56:29 +00:00
|
|
|
unsigned MakeReg(EVT VT);
|
2005-01-07 07:46:03 +00:00
|
|
|
|
2005-05-13 07:23:03 +00:00
|
|
|
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
|
2008-08-23 02:25:05 +00:00
|
|
|
virtual void InstructionSelect() = 0;
|
2008-06-30 20:45:06 +00:00
|
|
|
|
2008-08-21 16:06:51 +00:00
|
|
|
void SelectRootInit() {
|
2008-09-30 18:30:35 +00:00
|
|
|
DAGSize = CurDAG->AssignTopologicalOrder();
|
2006-08-07 22:16:08 +00:00
|
|
|
}
|
2005-04-21 20:39:54 +00:00
|
|
|
|
2006-02-24 02:12:52 +00:00
|
|
|
/// SelectInlineAsmMemoryOperand - Select the specified address as a target
|
|
|
|
/// addressing mode, according to the specified constraint code. If this does
|
|
|
|
/// not match or is not implemented, return true. The resultant operands
|
|
|
|
/// (which will appear in the machine instruction) should be added to the
|
|
|
|
/// OutOps vector.
|
2008-07-27 21:46:04 +00:00
|
|
|
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
|
2006-02-24 02:12:52 +00:00
|
|
|
char ConstraintCode,
|
2008-08-23 02:25:05 +00:00
|
|
|
std::vector<SDValue> &OutOps) {
|
2006-02-24 02:12:52 +00:00
|
|
|
return true;
|
|
|
|
}
|
2006-07-27 06:36:49 +00:00
|
|
|
|
2008-11-27 00:49:46 +00:00
|
|
|
/// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
|
|
|
|
/// U can be folded during instruction selection that starts at Root and
|
|
|
|
/// folding N is profitable.
|
|
|
|
virtual
|
2009-05-08 18:51:58 +00:00
|
|
|
bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
|
|
|
|
|
2006-08-01 18:29:48 +00:00
|
|
|
/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
|
|
|
|
/// to use for this target when scheduling the DAG.
|
2009-01-15 22:18:12 +00:00
|
|
|
virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
|
2006-08-01 18:29:48 +00:00
|
|
|
|
2005-08-18 18:44:33 +00:00
|
|
|
protected:
|
2008-07-01 18:49:06 +00:00
|
|
|
/// DAGSize - Size of DAG being instruction selected.
|
|
|
|
///
|
|
|
|
unsigned DAGSize;
|
|
|
|
|
2006-02-24 02:12:52 +00:00
|
|
|
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
|
|
|
|
/// by tblgen. Others should not call it.
|
2008-08-23 02:25:05 +00:00
|
|
|
void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
|
2006-07-27 06:36:49 +00:00
|
|
|
|
2006-10-11 03:58:02 +00:00
|
|
|
// Calls to these predicates are generated by tblgen.
|
2008-07-27 21:46:04 +00:00
|
|
|
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
|
2007-07-24 23:00:27 +00:00
|
|
|
int64_t DesiredMaskS) const;
|
2008-07-27 21:46:04 +00:00
|
|
|
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
|
2007-07-24 23:00:27 +00:00
|
|
|
int64_t DesiredMaskS) const;
|
2006-10-11 03:58:02 +00:00
|
|
|
|
2009-10-29 22:30:23 +00:00
|
|
|
// Calls to these functions are generated by tblgen.
|
2010-01-05 01:24:18 +00:00
|
|
|
SDNode *Select_INLINEASM(SDNode *N);
|
|
|
|
SDNode *Select_UNDEF(SDNode *N);
|
|
|
|
SDNode *Select_EH_LABEL(SDNode *N);
|
|
|
|
void CannotYetSelect(SDNode *N);
|
|
|
|
void CannotYetSelectIntrinsic(SDNode *N);
|
2009-10-29 22:30:23 +00:00
|
|
|
|
2005-01-17 17:14:43 +00:00
|
|
|
private:
|
2008-09-23 21:53:34 +00:00
|
|
|
void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
|
2008-10-14 23:54:11 +00:00
|
|
|
MachineModuleInfo *MMI,
|
2009-01-13 00:35:13 +00:00
|
|
|
DwarfWriter *DW,
|
2008-10-14 23:54:11 +00:00
|
|
|
const TargetInstrInfo &TII);
|
2008-08-27 23:52:12 +00:00
|
|
|
void FinishBasicBlock();
|
2005-04-21 20:39:54 +00:00
|
|
|
|
2008-08-23 02:25:05 +00:00
|
|
|
void SelectBasicBlock(BasicBlock *LLVMBB,
|
|
|
|
BasicBlock::iterator Begin,
|
2009-11-20 02:51:26 +00:00
|
|
|
BasicBlock::iterator End,
|
|
|
|
bool &HadTailCall);
|
2008-08-23 02:25:05 +00:00
|
|
|
void CodeGenAndEmitDAG();
|
2008-08-27 23:52:12 +00:00
|
|
|
void LowerArguments(BasicBlock *BB);
|
2008-06-17 06:09:18 +00:00
|
|
|
|
2008-08-23 02:25:05 +00:00
|
|
|
void ComputeLiveOutVRegInfo();
|
|
|
|
|
2008-08-27 23:52:12 +00:00
|
|
|
void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
|
2006-03-27 01:32:24 +00:00
|
|
|
|
2008-09-03 23:12:08 +00:00
|
|
|
bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
|
|
|
|
|
2009-02-06 18:26:51 +00:00
|
|
|
/// Create the scheduler. If a specific scheduler was specified
|
|
|
|
/// via the SchedulerRegistry, use it, otherwise select the
|
|
|
|
/// one preferred by the target.
|
|
|
|
///
|
2009-02-11 04:27:20 +00:00
|
|
|
ScheduleDAGSDNodes *CreateScheduler();
|
2005-01-07 07:46:03 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */
|