2002-11-22 22:42:50 +00:00
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//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
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2005-04-21 23:38:14 +00:00
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//
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2003-10-20 19:43:21 +00:00
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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2005-04-21 23:38:14 +00:00
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//
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2003-10-20 19:43:21 +00:00
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//===----------------------------------------------------------------------===//
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2002-10-25 22:55:53 +00:00
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//
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2003-01-14 22:00:31 +00:00
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// This file contains the X86 implementation of the TargetInstrInfo class.
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2002-10-25 22:55:53 +00:00
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//
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//===----------------------------------------------------------------------===//
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2002-10-29 21:05:24 +00:00
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#include "X86InstrInfo.h"
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2002-12-03 05:42:53 +00:00
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#include "X86.h"
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2006-05-30 21:45:53 +00:00
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#include "X86GenInstrInfo.inc"
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2005-01-02 02:37:07 +00:00
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#include "X86InstrBuilder.h"
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2006-05-30 21:45:53 +00:00
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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2003-05-24 00:09:50 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2003-11-11 22:41:34 +00:00
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using namespace llvm;
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2006-05-30 21:45:53 +00:00
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X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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: TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])),
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2006-09-08 06:48:29 +00:00
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TM(tm), RI(tm, *this) {
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2002-10-25 22:55:53 +00:00
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}
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2006-10-17 22:41:45 +00:00
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/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
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/// instruction if it has one. This is used by codegen passes that update
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/// DWARF line number info as they modify the code.
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unsigned X86InstrInfo::getDWARF_LABELOpcode() const {
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return X86::DWARF_LABEL;
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}
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2002-10-25 22:55:53 +00:00
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2003-12-28 17:35:08 +00:00
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bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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2006-09-08 06:48:29 +00:00
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if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
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oc == X86::MOV32rr || oc == X86::MOV64rr ||
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2006-05-08 08:01:26 +00:00
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oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
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2006-02-01 23:03:16 +00:00
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oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
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2006-02-16 22:45:17 +00:00
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oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
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2006-03-21 07:09:35 +00:00
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oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
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2006-04-03 20:53:28 +00:00
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oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
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oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
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oc == X86::MOVDI2PDIrr || oc == X86::MOVQI2PQIrr ||
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oc == X86::MOVPDI2DIrr) {
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2003-12-28 17:35:08 +00:00
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid register-register move instruction");
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2004-02-13 21:01:20 +00:00
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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2003-12-28 17:35:08 +00:00
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return true;
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}
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return false;
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}
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2004-07-31 09:38:47 +00:00
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2006-02-02 20:12:32 +00:00
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unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case X86::MOV8rm:
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case X86::MOV16rm:
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2006-05-11 07:33:49 +00:00
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case X86::MOV16_rm:
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2006-02-02 20:12:32 +00:00
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case X86::MOV32rm:
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2006-05-11 07:33:49 +00:00
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case X86::MOV32_rm:
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2006-09-08 06:48:29 +00:00
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case X86::MOV64rm:
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2006-02-02 20:12:32 +00:00
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case X86::FpLD64m:
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case X86::MOVSSrm:
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case X86::MOVSDrm:
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2006-04-18 16:44:51 +00:00
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case X86::MOVAPSrm:
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case X86::MOVAPDrm:
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2006-02-02 20:12:32 +00:00
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if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
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MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
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MI->getOperand(2).getImmedValue() == 1 &&
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MI->getOperand(3).getReg() == 0 &&
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MI->getOperand(4).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case X86::MOV8mr:
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case X86::MOV16mr:
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2006-05-11 07:33:49 +00:00
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case X86::MOV16_mr:
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2006-02-02 20:12:32 +00:00
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case X86::MOV32mr:
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2006-05-11 07:33:49 +00:00
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case X86::MOV32_mr:
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2006-09-08 06:48:29 +00:00
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case X86::MOV64mr:
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2006-02-02 20:12:32 +00:00
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case X86::FpSTP64m:
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case X86::MOVSSmr:
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case X86::MOVSDmr:
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2006-04-18 16:44:51 +00:00
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case X86::MOVAPSmr:
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case X86::MOVAPDmr:
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2006-02-02 20:12:32 +00:00
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if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
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MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
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2006-02-02 20:38:12 +00:00
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MI->getOperand(1).getImmedValue() == 1 &&
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MI->getOperand(2).getReg() == 0 &&
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MI->getOperand(3).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(0).getFrameIndex();
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2006-02-02 20:12:32 +00:00
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return MI->getOperand(4).getReg();
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}
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break;
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}
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return 0;
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}
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2005-01-02 02:37:07 +00:00
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// three-address instruction on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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///
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MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
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// All instructions input are two-addr instructions. Get the known operands.
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Src = MI->getOperand(1).getReg();
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2006-05-30 20:26:50 +00:00
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switch (MI->getOpcode()) {
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default: break;
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case X86::SHUFPSrri: {
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assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
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2006-05-30 21:30:59 +00:00
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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2006-05-30 21:45:53 +00:00
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unsigned A = MI->getOperand(0).getReg();
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unsigned B = MI->getOperand(1).getReg();
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unsigned C = MI->getOperand(2).getReg();
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unsigned M = MI->getOperand(3).getImmedValue();
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2006-05-30 22:13:36 +00:00
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if (!Subtarget->hasSSE2() || B != C) return 0;
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2006-05-30 21:45:53 +00:00
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return BuildMI(X86::PSHUFDri, 2, A).addReg(B).addImm(M);
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2006-05-30 20:26:50 +00:00
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}
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}
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2005-04-21 23:38:14 +00:00
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// FIXME: None of these instructions are promotable to LEAs without
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// additional information. In particular, LEA doesn't set the flags that
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2005-01-02 04:18:17 +00:00
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// add and inc do. :(
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return 0;
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2005-01-02 02:37:07 +00:00
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// FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
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// we have subtarget support, enable the 16-bit LEA generation here.
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bool DisableLEA16 = true;
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switch (MI->getOpcode()) {
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case X86::INC32r:
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2006-09-08 06:48:29 +00:00
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case X86::INC64_32r:
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2005-01-02 02:37:07 +00:00
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assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
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return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
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case X86::INC16r:
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2006-09-08 06:48:29 +00:00
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case X86::INC64_16r:
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2005-01-02 02:37:07 +00:00
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
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return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
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case X86::DEC32r:
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2006-09-08 06:48:29 +00:00
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case X86::DEC64_32r:
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2005-01-02 02:37:07 +00:00
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assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
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return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
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case X86::DEC16r:
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2006-09-08 06:48:29 +00:00
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case X86::DEC64_16r:
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2005-01-02 02:37:07 +00:00
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
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return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
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case X86::ADD32rr:
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
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MI->getOperand(2).getReg());
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case X86::ADD16rr:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
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MI->getOperand(2).getReg());
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case X86::ADD32ri:
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2006-05-19 18:43:41 +00:00
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case X86::ADD32ri8:
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2005-01-02 02:37:07 +00:00
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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if (MI->getOperand(2).isImmediate())
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return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
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MI->getOperand(2).getImmedValue());
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return 0;
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case X86::ADD16ri:
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2006-05-19 18:43:41 +00:00
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case X86::ADD16ri8:
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2005-01-02 02:37:07 +00:00
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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if (MI->getOperand(2).isImmediate())
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return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
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MI->getOperand(2).getImmedValue());
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break;
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case X86::SHL16ri:
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if (DisableLEA16) return 0;
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case X86::SHL32ri:
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assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
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"Unknown shl instruction!");
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unsigned ShAmt = MI->getOperand(2).getImmedValue();
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if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
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X86AddressMode AM;
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AM.Scale = 1 << ShAmt;
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AM.IndexReg = Src;
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unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
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return addFullAddress(BuildMI(Opc, 5, Dest), AM);
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}
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break;
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}
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return 0;
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}
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Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-19 07:11:01 +00:00
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commute them.
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///
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MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
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2006-09-28 23:33:12 +00:00
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// FIXME: Can commute cmoves by changing the condition!
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Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-19 07:11:01 +00:00
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switch (MI->getOpcode()) {
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2005-01-19 07:31:24 +00:00
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case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
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case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
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Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-19 07:11:01 +00:00
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case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
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case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
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2005-01-19 07:31:24 +00:00
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unsigned Opc;
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unsigned Size;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
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case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
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case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
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case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
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}
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Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-19 07:11:01 +00:00
|
|
|
unsigned Amt = MI->getOperand(3).getImmedValue();
|
|
|
|
unsigned A = MI->getOperand(0).getReg();
|
|
|
|
unsigned B = MI->getOperand(1).getReg();
|
|
|
|
unsigned C = MI->getOperand(2).getReg();
|
2005-01-19 16:55:52 +00:00
|
|
|
return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
|
Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-19 07:11:01 +00:00
|
|
|
}
|
|
|
|
default:
|
|
|
|
return TargetInstrInfo::commuteInstruction(MI);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-10-20 17:42:20 +00:00
|
|
|
static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
|
|
|
|
switch (BrOpc) {
|
|
|
|
default: return X86::COND_INVALID;
|
|
|
|
case X86::JE: return X86::COND_E;
|
|
|
|
case X86::JNE: return X86::COND_NE;
|
|
|
|
case X86::JL: return X86::COND_L;
|
|
|
|
case X86::JLE: return X86::COND_LE;
|
|
|
|
case X86::JG: return X86::COND_G;
|
|
|
|
case X86::JGE: return X86::COND_GE;
|
|
|
|
case X86::JB: return X86::COND_B;
|
|
|
|
case X86::JBE: return X86::COND_BE;
|
|
|
|
case X86::JA: return X86::COND_A;
|
|
|
|
case X86::JAE: return X86::COND_AE;
|
|
|
|
case X86::JS: return X86::COND_S;
|
|
|
|
case X86::JNS: return X86::COND_NS;
|
|
|
|
case X86::JP: return X86::COND_P;
|
|
|
|
case X86::JNP: return X86::COND_NP;
|
|
|
|
case X86::JO: return X86::COND_O;
|
|
|
|
case X86::JNO: return X86::COND_NO;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
|
|
|
|
switch (CC) {
|
|
|
|
default: assert(0 && "Illegal condition code!");
|
|
|
|
case X86::COND_E: return X86::JE;
|
|
|
|
case X86::COND_NE: return X86::JNE;
|
|
|
|
case X86::COND_L: return X86::JL;
|
|
|
|
case X86::COND_LE: return X86::JLE;
|
|
|
|
case X86::COND_G: return X86::JG;
|
|
|
|
case X86::COND_GE: return X86::JGE;
|
|
|
|
case X86::COND_B: return X86::JB;
|
|
|
|
case X86::COND_BE: return X86::JBE;
|
|
|
|
case X86::COND_A: return X86::JA;
|
|
|
|
case X86::COND_AE: return X86::JAE;
|
|
|
|
case X86::COND_S: return X86::JS;
|
|
|
|
case X86::COND_NS: return X86::JNS;
|
|
|
|
case X86::COND_P: return X86::JP;
|
|
|
|
case X86::COND_NP: return X86::JNP;
|
|
|
|
case X86::COND_O: return X86::JO;
|
|
|
|
case X86::COND_NO: return X86::JNO;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-10-21 05:52:40 +00:00
|
|
|
/// GetOppositeBranchCondition - Return the inverse of the specified condition,
|
|
|
|
/// e.g. turning COND_E to COND_NE.
|
|
|
|
X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
|
|
|
|
switch (CC) {
|
|
|
|
default: assert(0 && "Illegal condition code!");
|
|
|
|
case X86::COND_E: return X86::COND_NE;
|
|
|
|
case X86::COND_NE: return X86::COND_E;
|
|
|
|
case X86::COND_L: return X86::COND_GE;
|
|
|
|
case X86::COND_LE: return X86::COND_G;
|
|
|
|
case X86::COND_G: return X86::COND_LE;
|
|
|
|
case X86::COND_GE: return X86::COND_L;
|
|
|
|
case X86::COND_B: return X86::COND_AE;
|
|
|
|
case X86::COND_BE: return X86::COND_A;
|
|
|
|
case X86::COND_A: return X86::COND_BE;
|
|
|
|
case X86::COND_AE: return X86::COND_B;
|
|
|
|
case X86::COND_S: return X86::COND_NS;
|
|
|
|
case X86::COND_NS: return X86::COND_S;
|
|
|
|
case X86::COND_P: return X86::COND_NP;
|
|
|
|
case X86::COND_NP: return X86::COND_P;
|
|
|
|
case X86::COND_O: return X86::COND_NO;
|
|
|
|
case X86::COND_NO: return X86::COND_O;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-10-20 17:42:20 +00:00
|
|
|
bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock *&TBB,
|
|
|
|
MachineBasicBlock *&FBB,
|
|
|
|
std::vector<MachineOperand> &Cond) const {
|
|
|
|
// TODO: If FP_REG_KILL is around, ignore it.
|
|
|
|
|
|
|
|
// If the block has no terminators, it just falls into the block after it.
|
|
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
|
|
if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Get the last instruction in the block.
|
|
|
|
MachineInstr *LastInst = I;
|
|
|
|
|
|
|
|
// If there is only one terminator instruction, process it.
|
|
|
|
if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
|
|
|
|
if (!isBranch(LastInst->getOpcode()))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If the block ends with a branch there are 3 possibilities:
|
|
|
|
// it's an unconditional, conditional, or indirect branch.
|
|
|
|
|
|
|
|
if (LastInst->getOpcode() == X86::JMP) {
|
|
|
|
TBB = LastInst->getOperand(0).getMachineBasicBlock();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
|
|
|
|
if (BranchCode == X86::COND_INVALID)
|
|
|
|
return true; // Can't handle indirect branch.
|
|
|
|
|
|
|
|
// Otherwise, block ends with fall-through condbranch.
|
|
|
|
TBB = LastInst->getOperand(0).getMachineBasicBlock();
|
|
|
|
Cond.push_back(MachineOperand::CreateImm(BranchCode));
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Get the instruction before it if it's a terminator.
|
|
|
|
MachineInstr *SecondLastInst = I;
|
|
|
|
|
|
|
|
// If there are three terminators, we don't know what sort of block this is.
|
|
|
|
if (SecondLastInst && I != MBB.begin() &&
|
|
|
|
isTerminatorInstr((--I)->getOpcode()))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If the block ends with X86::JMP and a COND_BRANCH, handle it.
|
|
|
|
X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
|
|
|
|
if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
|
|
|
|
TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
|
|
|
|
Cond.push_back(MachineOperand::CreateImm(BranchCode));
|
|
|
|
FBB = LastInst->getOperand(0).getMachineBasicBlock();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, can't handle this.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
|
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
|
|
if (I == MBB.begin()) return;
|
|
|
|
--I;
|
|
|
|
if (I->getOpcode() != X86::JMP &&
|
|
|
|
GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Remove the branch.
|
|
|
|
I->eraseFromParent();
|
|
|
|
|
|
|
|
I = MBB.end();
|
|
|
|
|
|
|
|
if (I == MBB.begin()) return;
|
|
|
|
--I;
|
|
|
|
if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Remove the branch.
|
|
|
|
I->eraseFromParent();
|
|
|
|
}
|
|
|
|
|
|
|
|
void X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
|
|
MachineBasicBlock *FBB,
|
|
|
|
const std::vector<MachineOperand> &Cond) const {
|
|
|
|
// Shouldn't be a fall through.
|
|
|
|
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
2006-10-21 05:34:23 +00:00
|
|
|
assert((Cond.size() == 1 || Cond.size() == 0) &&
|
|
|
|
"X86 branch conditions have one component!");
|
|
|
|
|
|
|
|
if (FBB == 0) { // One way branch.
|
|
|
|
if (Cond.empty()) {
|
|
|
|
// Unconditional branch?
|
|
|
|
BuildMI(&MBB, X86::JMP, 1).addMBB(TBB);
|
|
|
|
} else {
|
|
|
|
// Conditional branch.
|
|
|
|
unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
|
|
|
|
BuildMI(&MBB, Opc, 1).addMBB(TBB);
|
|
|
|
}
|
2006-10-20 17:42:20 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2006-10-21 05:42:09 +00:00
|
|
|
// Two-way Conditional branch.
|
2006-10-20 17:42:20 +00:00
|
|
|
unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
|
|
|
|
BuildMI(&MBB, Opc, 1).addMBB(TBB);
|
2006-10-21 05:42:09 +00:00
|
|
|
BuildMI(&MBB, X86::JMP, 1).addMBB(FBB);
|
2006-10-20 17:42:20 +00:00
|
|
|
}
|
|
|
|
|
2006-10-28 17:29:57 +00:00
|
|
|
bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
|
|
|
|
if (MBB.empty()) return false;
|
|
|
|
|
|
|
|
switch (MBB.back().getOpcode()) {
|
|
|
|
case X86::JMP: // Uncond branch.
|
|
|
|
case X86::JMP32r: // Indirect branch.
|
|
|
|
case X86::JMP32m: // Indirect branch through mem.
|
|
|
|
return true;
|
|
|
|
default: return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-10-20 17:42:20 +00:00
|
|
|
bool X86InstrInfo::
|
|
|
|
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
|
2006-10-21 05:52:40 +00:00
|
|
|
assert(Cond.size() == 1 && "Invalid X86 branch condition!");
|
|
|
|
Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
|
|
|
|
return false;
|
2006-10-20 17:42:20 +00:00
|
|
|
}
|
|
|
|
|
2006-09-08 06:48:29 +00:00
|
|
|
const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
|
|
|
|
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (Subtarget->is64Bit())
|
|
|
|
return &X86::GR64RegClass;
|
|
|
|
else
|
|
|
|
return &X86::GR32RegClass;
|
|
|
|
}
|