2007-06-06 07:42:06 +00:00
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//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-lower"
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#include "MipsISelLowering.h"
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2007-08-28 05:08:16 +00:00
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#include "MipsMachineFunction.h"
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2007-06-06 07:42:06 +00:00
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#include "MipsTargetMachine.h"
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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#include "MipsSubtarget.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 04:13:23 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/Debug.h"
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#include <queue>
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#include <set>
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using namespace llvm;
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const char *MipsTargetLowering::
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getTargetNodeName(unsigned Opcode) const
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{
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switch (Opcode)
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{
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2008-06-06 00:58:26 +00:00
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case MipsISD::JmpLink : return "MipsISD::JmpLink";
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case MipsISD::Hi : return "MipsISD::Hi";
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case MipsISD::Lo : return "MipsISD::Lo";
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case MipsISD::Ret : return "MipsISD::Ret";
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case MipsISD::SelectCC : return "MipsISD::SelectCC";
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
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case MipsISD::FPCmp : return "MipsISD::FPCmp";
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2008-06-06 00:58:26 +00:00
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default : return NULL;
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2007-06-06 07:42:06 +00:00
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}
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}
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MipsTargetLowering::
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MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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{
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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2007-06-06 07:42:06 +00:00
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// Mips does not have i1 type, so use i32 for
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// setcc operations results (slt, sgt, ...).
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setSetCCResultContents(ZeroOrOneSetCCResult);
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2007-11-12 19:49:57 +00:00
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// JumpTable targets must use GOT when using PIC_
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setUsesGlobalOffsetTable(true);
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2007-06-06 07:42:06 +00:00
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// Set up the register classes
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addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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// When dealing with single precision only, use libcalls
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if (!Subtarget->isSingleFloat()) {
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addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
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if (!Subtarget->isFP64bit())
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addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
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} else
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addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
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2007-06-06 07:42:06 +00:00
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// Load extented operations for i1 types must be promoted
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setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
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2008-07-09 04:15:08 +00:00
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// Mips Custom Operations
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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// Operations not directly supported by Mips.
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2008-07-07 19:11:24 +00:00
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setConvertAction(MVT::f64, MVT::f32, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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2008-07-09 04:15:08 +00:00
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::CTLZ, MVT::i32, Expand);
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setOperationAction(ISD::ROTL, MVT::i32, Expand);
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setOperationAction(ISD::ROTR, MVT::i32, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
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setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
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// Use the default for now
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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2008-07-07 19:11:24 +00:00
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if (Subtarget->isSingleFloat())
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setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
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2007-06-06 07:42:06 +00:00
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|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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if (!Subtarget->isAllegrex()) {
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2008-07-09 04:15:08 +00:00
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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}
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2007-06-06 07:42:06 +00:00
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setStackPointerRegisterToSaveRestore(Mips::SP);
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computeRegisterProperties();
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}
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2008-06-06 12:08:01 +00:00
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MVT MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
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2008-03-10 15:42:14 +00:00
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return MVT::i32;
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}
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2007-06-06 07:42:06 +00:00
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SDOperand MipsTargetLowering::
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LowerOperation(SDOperand Op, SelectionDAG &DAG)
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{
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switch (Op.getOpcode())
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{
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case ISD::CALL: return LowerCALL(Op, DAG);
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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2007-07-11 17:19:51 +00:00
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case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
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2007-11-12 19:49:57 +00:00
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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2008-07-09 04:15:08 +00:00
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case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
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2008-06-06 00:58:26 +00:00
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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2007-06-06 07:42:06 +00:00
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}
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return SDOperand();
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}
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2008-06-06 00:58:26 +00:00
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MachineBasicBlock *
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MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB)
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{
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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switch (MI->getOpcode()) {
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default: assert(false && "Unexpected instr type to insert");
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case Mips::Select_CC: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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2008-07-07 23:14:23 +00:00
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MachineFunction::iterator It = BB;
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2008-06-06 00:58:26 +00:00
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// setcc r1, r2, r3
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// bNE r1, r0, copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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2008-07-07 23:14:23 +00:00
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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2008-06-06 00:58:26 +00:00
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BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
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.addReg(Mips::ZERO).addMBB(sinkMBB);
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2008-07-07 23:14:23 +00:00
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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2008-06-06 00:58:26 +00:00
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// Update machine-CFG edges by first adding all successors of the current
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// block to the new block which will contain the Phi node for the select.
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for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
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e = BB->succ_end(); i != e; ++i)
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sinkMBB->addSuccessor(*i);
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// Next, remove all successors of the current block, and add the true
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|
|
// and fallthrough blocks as its successors.
|
|
|
|
while(!BB->succ_empty())
|
|
|
|
BB->removeSuccessor(BB->succ_begin());
|
|
|
|
BB->addSuccessor(copy0MBB);
|
|
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
|
|
|
|
// copy0MBB:
|
|
|
|
// %FalseValue = ...
|
|
|
|
// # fallthrough to sinkMBB
|
|
|
|
BB = copy0MBB;
|
|
|
|
|
|
|
|
// Update machine-CFG edges
|
|
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
|
|
|
|
// sinkMBB:
|
|
|
|
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
|
|
|
// ...
|
|
|
|
BB = sinkMBB;
|
|
|
|
BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
|
|
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
|
|
|
|
.addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
|
|
|
|
|
2008-07-07 23:14:23 +00:00
|
|
|
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
2008-06-06 00:58:26 +00:00
|
|
|
return BB;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Lower helper functions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
// AddLiveIn - This helper function adds the specified physical register to the
|
|
|
|
// MachineFunction as a live in value. It also creates a corresponding
|
|
|
|
// virtual register for it.
|
|
|
|
static unsigned
|
|
|
|
AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
|
|
|
|
{
|
|
|
|
assert(RC->contains(PReg) && "Not the correct regclass!");
|
2007-12-31 04:13:23 +00:00
|
|
|
unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
|
|
|
|
MF.getRegInfo().addLiveIn(PReg, VReg);
|
2007-06-06 07:42:06 +00:00
|
|
|
return VReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Misc Lower Operation implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
SDOperand MipsTargetLowering::
|
|
|
|
LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
|
|
|
|
{
|
2007-10-09 03:15:11 +00:00
|
|
|
SDOperand ResNode;
|
2007-06-06 07:42:06 +00:00
|
|
|
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
|
|
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
|
2007-11-05 03:02:32 +00:00
|
|
|
bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_);
|
2007-08-18 02:16:30 +00:00
|
|
|
|
2007-11-05 03:02:32 +00:00
|
|
|
SDOperand HiPart;
|
|
|
|
if (!isPIC) {
|
2008-06-06 12:08:01 +00:00
|
|
|
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
|
2007-10-09 03:15:11 +00:00
|
|
|
SDOperand Ops[] = { GA };
|
2007-11-05 03:02:32 +00:00
|
|
|
HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
|
|
|
|
} else // Emit Load from Global Pointer
|
|
|
|
HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
|
2007-08-18 02:16:30 +00:00
|
|
|
|
2007-11-05 03:02:32 +00:00
|
|
|
// On functions and global targets not internal linked only
|
|
|
|
// a load from got/GP is necessary for PIC to work.
|
|
|
|
if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV))))
|
|
|
|
return HiPart;
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2007-11-05 03:02:32 +00:00
|
|
|
SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
|
|
|
|
ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
|
2007-10-09 03:15:11 +00:00
|
|
|
|
|
|
|
return ResNode;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2007-07-11 17:19:51 +00:00
|
|
|
SDOperand MipsTargetLowering::
|
|
|
|
LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
assert(0 && "TLS not implemented for MIPS.");
|
2008-03-30 18:22:13 +00:00
|
|
|
return SDOperand(); // Not reached
|
2007-07-11 17:19:51 +00:00
|
|
|
}
|
|
|
|
|
2008-06-06 00:58:26 +00:00
|
|
|
SDOperand MipsTargetLowering::
|
|
|
|
LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
SDOperand LHS = Op.getOperand(0);
|
|
|
|
SDOperand RHS = Op.getOperand(1);
|
|
|
|
SDOperand True = Op.getOperand(2);
|
|
|
|
SDOperand False = Op.getOperand(3);
|
|
|
|
SDOperand CC = Op.getOperand(4);
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
|
2008-06-06 00:58:26 +00:00
|
|
|
SDOperand Ops[] = { LHS, RHS, CC };
|
|
|
|
SDOperand SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3);
|
|
|
|
|
|
|
|
return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
|
|
|
|
SetCCRes, True, False);
|
|
|
|
}
|
|
|
|
|
2007-11-12 19:49:57 +00:00
|
|
|
SDOperand MipsTargetLowering::
|
|
|
|
LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
SDOperand ResNode;
|
|
|
|
SDOperand HiPart;
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = Op.getValueType();
|
2007-11-12 19:49:57 +00:00
|
|
|
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
|
|
|
|
SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
|
|
|
|
|
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
|
2008-06-06 12:08:01 +00:00
|
|
|
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
|
2007-11-12 19:49:57 +00:00
|
|
|
SDOperand Ops[] = { JTI };
|
|
|
|
HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
|
|
|
|
} else // Emit Load from Global Pointer
|
|
|
|
HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
|
|
|
|
|
|
|
|
SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
|
|
|
|
ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
|
|
|
|
|
|
|
|
return ResNode;
|
|
|
|
}
|
|
|
|
|
2008-07-09 04:15:08 +00:00
|
|
|
SDOperand MipsTargetLowering::
|
|
|
|
LowerConstantPool(SDOperand Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
assert(0 && "ConstantPool not implemented for MIPS.");
|
|
|
|
return SDOperand(); // Not reached
|
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Calling Convention Implementation
|
|
|
|
//
|
|
|
|
// The lower operations present on calling convention works on this order:
|
|
|
|
// LowerCALL (virt regs --> phys regs, virt regs --> stack)
|
|
|
|
// LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
|
|
|
|
// LowerRET (virt regs --> phys regs)
|
|
|
|
// LowerCALL (phys regs --> virt regs)
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#include "MipsGenCallingConv.inc"
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// CALL Calling Convention Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// Mips custom CALL implementation
|
|
|
|
SDOperand MipsTargetLowering::
|
|
|
|
LowerCALL(SDOperand Op, SelectionDAG &DAG)
|
|
|
|
{
|
2008-03-17 06:57:02 +00:00
|
|
|
unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// By now, only CallingConv::C implemented
|
2008-03-17 06:57:02 +00:00
|
|
|
switch (CallingConv) {
|
2007-06-06 07:42:06 +00:00
|
|
|
default:
|
|
|
|
assert(0 && "Unsupported calling convention");
|
|
|
|
case CallingConv::Fast:
|
|
|
|
case CallingConv::C:
|
|
|
|
return LowerCCCCallTo(Op, DAG, CallingConv);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// LowerCCCCallTo - functions arguments are copied from virtual
|
|
|
|
/// regs to (physical regs)/(stack frame), CALLSEQ_START and
|
|
|
|
/// CALLSEQ_END are emitted.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
/// TODO: isVarArg, isTailCall.
|
2007-06-06 07:42:06 +00:00
|
|
|
SDOperand MipsTargetLowering::
|
|
|
|
LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
|
|
|
|
{
|
2007-07-11 23:16:16 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
SDOperand Chain = Op.getOperand(0);
|
|
|
|
SDOperand Callee = Op.getOperand(4);
|
2007-07-11 23:16:16 +00:00
|
|
|
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
|
|
|
|
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Analyze operands of the call, assigning locations to each operand.
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
2007-07-11 23:16:16 +00:00
|
|
|
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
|
|
|
|
|
|
|
|
// To meet ABI, Mips must always allocate 16 bytes on
|
|
|
|
// the stack (even if less than 4 are used as arguments)
|
2008-06-06 12:08:01 +00:00
|
|
|
int VTsize = MVT(MVT::i32).getSizeInBits()/8;
|
2007-08-28 05:08:16 +00:00
|
|
|
MFI->CreateFixedObject(VTsize, (VTsize*3));
|
2007-07-11 23:16:16 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
|
|
|
|
|
|
|
|
// Get a count of how many bytes are to be pushed on the stack.
|
|
|
|
unsigned NumBytes = CCInfo.getNextStackOffset();
|
|
|
|
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
|
|
|
|
getPointerTy()));
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// With EABI is it possible to have 16 args on registers.
|
|
|
|
SmallVector<std::pair<unsigned, SDOperand>, 16> RegsToPass;
|
2007-06-06 07:42:06 +00:00
|
|
|
SmallVector<SDOperand, 8> MemOpChains;
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// First/LastArgStackLoc contains the first/last
|
|
|
|
// "at stack" argument location.
|
|
|
|
int LastArgStackLoc = 0;
|
|
|
|
unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Walk the register/memloc assignments, inserting copies/loads.
|
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
|
|
CCValAssign &VA = ArgLocs[i];
|
|
|
|
|
|
|
|
// Arguments start after the 5 first operands of ISD::CALL
|
|
|
|
SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
|
|
|
|
|
|
|
|
// Promote the value if needed.
|
|
|
|
switch (VA.getLocInfo()) {
|
2008-03-17 06:57:02 +00:00
|
|
|
default: assert(0 && "Unknown loc info!");
|
|
|
|
case CCValAssign::Full: break;
|
|
|
|
case CCValAssign::SExt:
|
|
|
|
Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
|
|
|
|
break;
|
|
|
|
case CCValAssign::ZExt:
|
|
|
|
Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
|
|
|
|
break;
|
|
|
|
case CCValAssign::AExt:
|
|
|
|
Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
|
|
|
|
break;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2007-11-05 03:02:32 +00:00
|
|
|
// Arguments that can be passed on register must be kept at
|
|
|
|
// RegsToPass vector
|
2007-06-06 07:42:06 +00:00
|
|
|
if (VA.isRegLoc()) {
|
|
|
|
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
2008-03-17 06:57:02 +00:00
|
|
|
continue;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2008-03-17 06:57:02 +00:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// Register cant get to this point...
|
2008-03-17 06:57:02 +00:00
|
|
|
assert(VA.isMemLoc());
|
|
|
|
|
|
|
|
// Create the frame index object for this incoming parameter
|
|
|
|
// This guarantees that when allocating Local Area the firsts
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// 16 bytes which are alwayes reserved won't be overwritten
|
|
|
|
// if O32 ABI is used. For EABI the first address is zero.
|
|
|
|
LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
|
2008-06-06 12:08:01 +00:00
|
|
|
int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
LastArgStackLoc);
|
2008-03-17 06:57:02 +00:00
|
|
|
|
|
|
|
SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
|
|
|
|
|
|
|
|
// emit ISD::STORE whichs stores the
|
|
|
|
// parameter value to a stack Location
|
|
|
|
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// Transform all store nodes into one single node because all store
|
|
|
|
// nodes are independent of each other.
|
2007-06-06 07:42:06 +00:00
|
|
|
if (!MemOpChains.empty())
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&MemOpChains[0], MemOpChains.size());
|
|
|
|
|
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token
|
|
|
|
// chain and flag operands which copy the outgoing args into registers.
|
|
|
|
// The InFlag in necessary since all emited instructions must be
|
|
|
|
// stuck together.
|
|
|
|
SDOperand InFlag;
|
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
|
|
|
Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
|
|
|
|
RegsToPass[i].second, InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
2007-10-09 03:15:11 +00:00
|
|
|
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
|
|
|
|
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
|
2007-11-05 03:02:32 +00:00
|
|
|
// node so that legalize doesn't hack it.
|
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
2007-06-06 07:42:06 +00:00
|
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
|
2007-10-09 03:15:11 +00:00
|
|
|
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
|
2007-06-06 07:42:06 +00:00
|
|
|
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
|
|
|
|
|
2007-11-05 03:02:32 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// MipsJmpLink = #chain, #target_address, #opt_in_flags...
|
|
|
|
// = Chain, Callee, Reg#1, Reg#2, ...
|
|
|
|
//
|
|
|
|
// Returns a chain & a flag for retval copy to use.
|
|
|
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
|
|
SmallVector<SDOperand, 8> Ops;
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(Callee);
|
|
|
|
|
|
|
|
// Add argument registers to the end of the list so that they are
|
|
|
|
// known live into the call.
|
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
|
|
|
|
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
|
|
|
|
RegsToPass[i].second.getValueType()));
|
|
|
|
|
|
|
|
if (InFlag.Val)
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
|
|
|
|
Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2008-06-04 01:45:25 +00:00
|
|
|
// Create the CALLSEQ_END node.
|
2008-06-01 03:49:39 +00:00
|
|
|
Chain = DAG.getCALLSEQ_END(Chain,
|
|
|
|
DAG.getConstant(NumBytes, getPointerTy()),
|
|
|
|
DAG.getConstant(0, getPointerTy()),
|
|
|
|
InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2007-11-05 03:02:32 +00:00
|
|
|
// Create a stack location to hold GP when PIC is used. This stack
|
|
|
|
// location is used on function prologue to save GP and also after all
|
|
|
|
// emited CALL's to restore GP.
|
|
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
|
|
|
|
// Function can have an arbitrary number of calls, so
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// hold the LastArgStackLoc with the biggest offset.
|
2007-11-05 03:02:32 +00:00
|
|
|
int FI;
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
|
|
|
|
LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
|
2007-11-05 03:02:32 +00:00
|
|
|
// Create the frame index only once. SPOffset here can be anything
|
|
|
|
// (this will be fixed on processFunctionBeforeFrameFinalized)
|
|
|
|
if (MipsFI->getGPStackOffset() == -1) {
|
|
|
|
FI = MFI->CreateFixedObject(4, 0);
|
|
|
|
MipsFI->setGPFI(FI);
|
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
MipsFI->setGPStackOffset(LastArgStackLoc);
|
2007-11-05 03:02:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Reload GP value.
|
|
|
|
FI = MipsFI->getGPFI();
|
|
|
|
SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
|
|
|
|
SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
|
|
|
|
Chain = GPLoad.getValue(1);
|
|
|
|
Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
|
|
|
|
GPLoad, SDOperand(0,0));
|
2008-06-01 03:49:39 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
2007-11-05 03:02:32 +00:00
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Handle result values, copying them out of physregs into vregs that we
|
|
|
|
// return.
|
|
|
|
return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// LowerCallResult - Lower the result values of an ISD::CALL into the
|
|
|
|
/// appropriate copies out of appropriate physical registers. This assumes that
|
|
|
|
/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
|
|
|
|
/// being lowered. Returns a SDNode with the same number of values as the
|
|
|
|
/// ISD::CALL.
|
|
|
|
SDNode *MipsTargetLowering::
|
|
|
|
LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
|
|
|
|
unsigned CallingConv, SelectionDAG &DAG) {
|
|
|
|
|
2007-07-11 23:16:16 +00:00
|
|
|
bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Assign locations to each value returned by this call.
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
2007-07-11 23:16:16 +00:00
|
|
|
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
|
|
|
|
SmallVector<SDOperand, 8> ResultVals;
|
|
|
|
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
|
|
Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
|
|
|
|
RVLocs[i].getValVT(), InFlag).getValue(1);
|
|
|
|
InFlag = Chain.getValue(2);
|
|
|
|
ResultVals.push_back(Chain.getValue(0));
|
|
|
|
}
|
|
|
|
|
|
|
|
ResultVals.push_back(Chain);
|
2007-11-05 03:02:32 +00:00
|
|
|
|
|
|
|
// Merge everything together with a MERGE_VALUES node.
|
2008-06-30 10:19:09 +00:00
|
|
|
return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
|
|
|
|
ResultVals.size()).Val;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// FORMAL_ARGUMENTS Calling Convention Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// Mips custom FORMAL_ARGUMENTS implementation
|
|
|
|
SDOperand MipsTargetLowering::
|
|
|
|
LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
|
|
|
switch(CC)
|
|
|
|
{
|
|
|
|
default:
|
|
|
|
assert(0 && "Unsupported calling convention");
|
|
|
|
case CallingConv::C:
|
|
|
|
return LowerCCCArguments(Op, DAG);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// LowerCCCArguments - transform physical registers into
|
|
|
|
/// virtual registers and generate load operations for
|
|
|
|
/// arguments places on the stack.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
/// TODO: isVarArg
|
2007-06-06 07:42:06 +00:00
|
|
|
SDOperand MipsTargetLowering::
|
|
|
|
LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
|
|
|
|
{
|
2007-07-11 23:16:16 +00:00
|
|
|
SDOperand Root = Op.getOperand(0);
|
2007-06-06 07:42:06 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2007-08-28 05:08:16 +00:00
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
2007-07-11 23:16:16 +00:00
|
|
|
|
|
|
|
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
|
|
|
|
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
|
|
|
|
|
|
|
|
unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2007-11-12 19:49:57 +00:00
|
|
|
// GP holds the GOT address on PIC calls.
|
|
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
|
|
|
|
AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Assign locations to all of the incoming arguments.
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
2007-07-11 23:16:16 +00:00
|
|
|
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
SmallVector<SDOperand, 16> ArgValues;
|
2007-07-11 23:16:16 +00:00
|
|
|
SDOperand StackPtr;
|
2007-06-06 07:42:06 +00:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
|
|
|
|
|
|
CCValAssign &VA = ArgLocs[i];
|
|
|
|
|
|
|
|
// Arguments stored on registers
|
|
|
|
if (VA.isRegLoc()) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT RegVT = VA.getLocVT();
|
2007-06-06 07:42:06 +00:00
|
|
|
TargetRegisterClass *RC;
|
|
|
|
|
|
|
|
if (RegVT == MVT::i32)
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
RC = Mips::CPURegsRegisterClass;
|
|
|
|
else if (RegVT == MVT::f32) {
|
|
|
|
if (Subtarget->isSingleFloat())
|
|
|
|
RC = Mips::FGR32RegisterClass;
|
|
|
|
else
|
|
|
|
RC = Mips::AFGR32RegisterClass;
|
|
|
|
} else if (RegVT == MVT::f64) {
|
|
|
|
if (!Subtarget->isSingleFloat())
|
|
|
|
RC = Mips::AFGR64RegisterClass;
|
|
|
|
} else
|
|
|
|
assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Transform the arguments stored on
|
|
|
|
// physical registers into virtual ones
|
2007-07-11 23:16:16 +00:00
|
|
|
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
|
2007-06-06 07:42:06 +00:00
|
|
|
SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
|
|
|
|
|
|
|
|
// If this is an 8 or 16-bit value, it is really passed promoted
|
|
|
|
// to 32 bits. Insert an assert[sz]ext to capture this, then
|
|
|
|
// truncate to the right size.
|
|
|
|
if (VA.getLocInfo() == CCValAssign::SExt)
|
|
|
|
ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
|
|
|
|
DAG.getValueType(VA.getValVT()));
|
|
|
|
else if (VA.getLocInfo() == CCValAssign::ZExt)
|
|
|
|
ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
|
|
|
|
DAG.getValueType(VA.getValVT()));
|
|
|
|
|
|
|
|
if (VA.getLocInfo() != CCValAssign::Full)
|
|
|
|
ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
|
|
|
|
|
|
|
|
ArgValues.push_back(ArgValue);
|
|
|
|
|
2007-07-11 23:16:16 +00:00
|
|
|
// To meet ABI, when VARARGS are passed on registers, the registers
|
2007-08-28 05:08:16 +00:00
|
|
|
// must have their values written to the caller stack frame.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
if ((isVarArg) && (Subtarget->isABI_O32())) {
|
2007-07-11 23:16:16 +00:00
|
|
|
if (StackPtr.Val == 0)
|
|
|
|
StackPtr = DAG.getRegister(StackReg, getPointerTy());
|
|
|
|
|
2007-08-28 05:08:16 +00:00
|
|
|
// The stack pointer offset is relative to the caller stack frame.
|
|
|
|
// Since the real stack size is unknown here, a negative SPOffset
|
|
|
|
// is used so there's a way to adjust these offsets when the stack
|
|
|
|
// size get known (on EliminateFrameIndex). A dummy SPOffset is
|
|
|
|
// used instead of a direct negative address (which is recorded to
|
|
|
|
// be used on emitPrologue) to avoid mis-calc of the first stack
|
|
|
|
// offset on PEI::calculateFrameObjectOffsets.
|
|
|
|
// Arguments are always 32-bit.
|
|
|
|
int FI = MFI->CreateFixedObject(4, 0);
|
|
|
|
MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
|
2007-07-11 23:16:16 +00:00
|
|
|
SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
|
|
|
|
|
|
|
|
// emit ISD::STORE whichs stores the
|
|
|
|
// parameter value to a stack Location
|
|
|
|
ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
} else { // VA.isRegLoc()
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// sanity check
|
|
|
|
assert(VA.isMemLoc());
|
|
|
|
|
2007-08-28 05:08:16 +00:00
|
|
|
// The stack pointer offset is relative to the caller stack frame.
|
|
|
|
// Since the real stack size is unknown here, a negative SPOffset
|
|
|
|
// is used so there's a way to adjust these offsets when the stack
|
|
|
|
// size get known (on EliminateFrameIndex). A dummy SPOffset is
|
|
|
|
// used instead of a direct negative address (which is recorded to
|
|
|
|
// be used on emitPrologue) to avoid mis-calc of the first stack
|
|
|
|
// offset on PEI::calculateFrameObjectOffsets.
|
|
|
|
// Arguments are always 32-bit.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
|
|
|
|
int FI = MFI->CreateFixedObject(ArgSize, 0);
|
|
|
|
MipsFI->recordLoadArgsFI(FI, -(ArgSize+
|
|
|
|
(FirstStackArgLoc + VA.getLocMemOffset())));
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Create load nodes to retrieve arguments from the stack
|
|
|
|
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
|
|
|
|
ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
|
|
|
|
}
|
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
|
|
|
|
// The mips ABIs for returning structs by value requires that we copy
|
|
|
|
// the sret argument into $v0 for the return. Save the argument into
|
|
|
|
// a virtual register so that we can access it from the return points.
|
|
|
|
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
|
|
|
|
unsigned Reg = MipsFI->getSRetReturnReg();
|
|
|
|
if (!Reg) {
|
|
|
|
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
|
|
|
|
MipsFI->setSRetReturnReg(Reg);
|
|
|
|
}
|
|
|
|
SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
|
|
|
|
Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
|
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
ArgValues.push_back(Root);
|
|
|
|
|
|
|
|
// Return the new list of results.
|
2008-06-30 10:19:09 +00:00
|
|
|
return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
|
|
|
|
ArgValues.size()).getValue(Op.ResNo);
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Return Value Calling Convention Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
SDOperand MipsTargetLowering::
|
|
|
|
LowerRET(SDOperand Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
// CCValAssign - represent the assignment of
|
|
|
|
// the return value to a location
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
2007-07-11 23:16:16 +00:00
|
|
|
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
|
|
|
|
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// CCState - Info about the registers and stack slot.
|
2007-07-11 23:16:16 +00:00
|
|
|
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Analize return values of ISD::RET
|
|
|
|
CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
|
|
|
|
|
|
|
|
// If this is the first return lowered for this function, add
|
|
|
|
// the regs to the liveout set for the function.
|
2007-12-31 04:13:23 +00:00
|
|
|
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
|
2007-06-06 07:42:06 +00:00
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i)
|
2007-07-11 23:16:16 +00:00
|
|
|
if (RVLocs[i].isRegLoc())
|
2007-12-31 04:13:23 +00:00
|
|
|
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// The chain is always operand #0
|
|
|
|
SDOperand Chain = Op.getOperand(0);
|
|
|
|
SDOperand Flag;
|
|
|
|
|
|
|
|
// Copy the result values into the output registers.
|
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
|
|
CCValAssign &VA = RVLocs[i];
|
|
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
|
|
|
|
// ISD::RET => ret chain, (regnum1,val1), ...
|
|
|
|
// So i*2+1 index only the regnums
|
2007-10-09 03:15:11 +00:00
|
|
|
Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// guarantee that all emitted copies are
|
|
|
|
// stuck together, avoiding something bad
|
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// The mips ABIs for returning structs by value requires that we copy
|
|
|
|
// the sret argument into $v0 for the return. We saved the argument into
|
|
|
|
// a virtual register in the entry block, so now we copy the value out
|
|
|
|
// and into $v0.
|
|
|
|
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
unsigned Reg = MipsFI->getSRetReturnReg();
|
|
|
|
|
|
|
|
if (!Reg)
|
|
|
|
assert(0 && "sret virtual register not created in the entry block");
|
|
|
|
SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
|
|
|
|
|
|
|
|
Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
|
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Return on Mips is always a "jr $ra"
|
|
|
|
if (Flag.Val)
|
|
|
|
return DAG.getNode(MipsISD::Ret, MVT::Other,
|
2007-10-09 03:15:11 +00:00
|
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
|
2007-06-06 07:42:06 +00:00
|
|
|
else // Return Void
|
|
|
|
return DAG.getNode(MipsISD::Ret, MVT::Other,
|
2007-10-09 03:15:11 +00:00
|
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32));
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2007-08-21 16:09:25 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Mips Inline Assembly Support
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
|
|
/// constraint it is for this target.
|
|
|
|
MipsTargetLowering::ConstraintType MipsTargetLowering::
|
|
|
|
getConstraintType(const std::string &Constraint) const
|
|
|
|
{
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// Mips specific constrainy
|
|
|
|
// GCC config/mips/constraints.md
|
|
|
|
//
|
|
|
|
// 'd' : An address register. Equivalent to r
|
|
|
|
// unless generating MIPS16 code.
|
|
|
|
// 'y' : Equivalent to r; retained for
|
|
|
|
// backwards compatibility.
|
2008-07-09 04:45:36 +00:00
|
|
|
// 'f' : Floating Point registers.
|
2007-08-21 16:09:25 +00:00
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
default : break;
|
|
|
|
case 'd':
|
|
|
|
case 'y':
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
case 'f':
|
2007-08-21 16:09:25 +00:00
|
|
|
return C_RegisterClass;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
|
|
|
|
/// return a list of registers that can be used to satisfy the constraint.
|
|
|
|
/// This should only be used for C_RegisterClass constraints.
|
2007-08-21 16:09:25 +00:00
|
|
|
std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
|
2008-06-06 12:08:01 +00:00
|
|
|
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
|
2007-08-21 16:09:25 +00:00
|
|
|
{
|
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
case 'r':
|
|
|
|
return std::make_pair(0U, Mips::CPURegsRegisterClass);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
case 'f':
|
2008-07-08 09:33:14 +00:00
|
|
|
if (VT == MVT::f32) {
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
if (Subtarget->isSingleFloat())
|
|
|
|
return std::make_pair(0U, Mips::FGR32RegisterClass);
|
|
|
|
else
|
|
|
|
return std::make_pair(0U, Mips::AFGR32RegisterClass);
|
2008-07-08 09:33:14 +00:00
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
if (VT == MVT::f64)
|
|
|
|
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
|
|
|
|
return std::make_pair(0U, Mips::AFGR64RegisterClass);
|
2007-08-21 16:09:25 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
/// Given a register class constraint, like 'r', if this corresponds directly
|
|
|
|
/// to an LLVM register class, return a register of 0 and the register class
|
|
|
|
/// pointer.
|
2007-08-21 16:09:25 +00:00
|
|
|
std::vector<unsigned> MipsTargetLowering::
|
|
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT) const
|
2007-08-21 16:09:25 +00:00
|
|
|
{
|
|
|
|
if (Constraint.size() != 1)
|
|
|
|
return std::vector<unsigned>();
|
|
|
|
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
default : break;
|
|
|
|
case 'r':
|
|
|
|
// GCC Mips Constraint Letters
|
|
|
|
case 'd':
|
|
|
|
case 'y':
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
|
|
|
|
Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
|
|
|
|
Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
|
|
|
|
Mips::T8, 0);
|
|
|
|
|
|
|
|
case 'f':
|
2008-07-08 09:33:14 +00:00
|
|
|
if (VT == MVT::f32) {
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
if (Subtarget->isSingleFloat())
|
|
|
|
return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
|
|
|
|
Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
|
|
|
|
Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
|
|
|
|
Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
|
|
|
|
Mips::F30, Mips::F31, 0);
|
|
|
|
else
|
|
|
|
return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
|
|
|
|
Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
|
|
|
|
Mips::F28, Mips::F30, 0);
|
2008-07-08 09:33:14 +00:00
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
|
|
|
|
if (VT == MVT::f64)
|
|
|
|
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
|
|
|
|
return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
|
|
|
|
Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
|
|
|
|
Mips::D14, Mips::D15, 0);
|
2007-08-21 16:09:25 +00:00
|
|
|
}
|
|
|
|
return std::vector<unsigned>();
|
|
|
|
}
|