2002-12-28 20:32:54 +00:00
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//===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===//
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2005-04-21 23:38:14 +00:00
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//
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2003-10-21 15:17:13 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 23:38:14 +00:00
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//
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2003-10-21 15:17:13 +00:00
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//===----------------------------------------------------------------------===//
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2002-10-25 22:55:53 +00:00
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//
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2008-02-10 18:45:23 +00:00
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// This file contains the X86 implementation of the TargetRegisterInfo class.
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2002-10-25 22:55:53 +00:00
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86REGISTERINFO_H
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#define X86REGISTERINFO_H
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2007-10-01 23:44:33 +00:00
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#include "llvm/ADT/DenseMap.h"
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2007-08-30 05:54:07 +00:00
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#include "llvm/ADT/SmallVector.h"
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2008-02-10 18:45:23 +00:00
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#include "llvm/Target/TargetRegisterInfo.h"
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2003-08-03 15:48:14 +00:00
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#include "X86GenRegisterInfo.h.inc"
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2002-12-25 05:06:43 +00:00
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2003-11-11 22:41:34 +00:00
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namespace llvm {
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2006-09-05 02:12:02 +00:00
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class Type;
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class TargetInstrInfo;
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2006-09-08 06:48:29 +00:00
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class X86TargetMachine;
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2003-11-11 22:41:34 +00:00
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2007-08-29 19:01:20 +00:00
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/// N86 namespace - Native X86 register numbers
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///
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namespace N86 {
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enum {
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EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
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};
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}
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2008-03-11 10:09:17 +00:00
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namespace X86 {
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/// SubregIndex - The index of various sized subregister classes. Note that
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/// these indices must be kept in sync with the class indices in the
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/// X86RegisterInfo.td file.
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enum SubregIndex {
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SUBREG_8BIT = 1, SUBREG_16BIT = 2, SUBREG_32BIT = 3
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};
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}
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2007-11-11 19:50:10 +00:00
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/// DWARFFlavour - Flavour of dwarf regnumbers
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///
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namespace DWARFFlavour {
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enum {
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2008-01-25 00:34:13 +00:00
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X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
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2007-11-11 19:50:10 +00:00
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};
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}
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2006-11-05 19:31:28 +00:00
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class X86RegisterInfo : public X86GenRegisterInfo {
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public:
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2006-09-08 06:48:29 +00:00
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X86TargetMachine &TM;
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2006-09-05 02:12:02 +00:00
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const TargetInstrInfo &TII;
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2006-11-05 19:31:28 +00:00
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2006-09-08 06:48:29 +00:00
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private:
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/// Is64Bit - Is the target 64-bits.
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2007-10-01 23:44:33 +00:00
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///
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2006-09-08 06:48:29 +00:00
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bool Is64Bit;
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2008-03-22 21:04:01 +00:00
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/// IsWin64 - Is the target on of win64 flavours
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///
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bool IsWin64;
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2006-09-08 06:48:29 +00:00
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/// SlotSize - Stack slot size in bytes.
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2007-10-01 23:44:33 +00:00
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///
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2006-09-08 06:48:29 +00:00
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unsigned SlotSize;
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2007-11-05 07:30:01 +00:00
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/// StackAlign - Default stack alignment.
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///
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unsigned StackAlign;
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2006-09-08 06:48:29 +00:00
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/// StackPtr - X86 physical register used as stack ptr.
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2007-10-01 23:44:33 +00:00
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///
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2006-09-08 06:48:29 +00:00
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unsigned StackPtr;
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/// FramePtr - X86 physical register used as frame ptr.
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2007-10-01 23:44:33 +00:00
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///
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2006-09-08 06:48:29 +00:00
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unsigned FramePtr;
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public:
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X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
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2002-12-25 05:06:43 +00:00
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2007-08-29 19:01:20 +00:00
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/// getX86RegNum - Returns the native X86 register number for the given LLVM
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/// register identifier.
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2008-04-16 20:10:13 +00:00
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static unsigned getX86RegNum(unsigned RegNo);
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2007-08-29 19:01:20 +00:00
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2008-01-01 21:11:32 +00:00
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unsigned getStackAlignment() const { return StackAlign; }
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2007-11-07 00:25:05 +00:00
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/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
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/// (created by TableGen) for target dependencies.
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2007-11-13 19:13:01 +00:00
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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2007-11-07 00:25:05 +00:00
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2002-12-28 20:32:54 +00:00
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/// Code Generation virtual methods...
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2008-01-04 23:57:37 +00:00
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///
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2007-09-26 21:31:07 +00:00
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const;
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2007-01-02 21:33:40 +00:00
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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2006-05-18 00:12:58 +00:00
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/// callee-save registers on this target.
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2007-07-14 14:06:15 +00:00
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const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
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2006-05-18 00:12:58 +00:00
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2007-01-02 21:33:40 +00:00
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/// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
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2006-05-18 00:12:58 +00:00
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/// register classes to spill each callee-saved register with. The order and
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2007-01-02 21:33:40 +00:00
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/// length of this list match the getCalleeSavedRegs() list.
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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const TargetRegisterClass* const*
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getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
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2004-02-17 04:33:18 +00:00
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2007-02-19 21:49:54 +00:00
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses and
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/// should be considered unavailable at all times, e.g. SP, RA. This is used by
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/// register scavenger to determine what registers are free.
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BitVector getReservedRegs(const MachineFunction &MF) const;
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2007-01-23 00:57:47 +00:00
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bool hasFP(const MachineFunction &MF) const;
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2007-07-19 00:42:05 +00:00
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bool hasReservedCallFrame(MachineFunction &MF) const;
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2004-02-14 19:49:54 +00:00
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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2002-12-13 09:54:12 +00:00
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2007-02-28 00:21:17 +00:00
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void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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2007-05-01 09:13:03 +00:00
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int SPAdj, RegScavenger *RS = NULL) const;
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2002-11-20 18:59:43 +00:00
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2004-02-14 19:49:54 +00:00
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void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
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2002-12-03 23:11:21 +00:00
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2004-02-14 19:49:54 +00:00
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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2006-03-23 18:12:57 +00:00
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2006-03-28 13:48:33 +00:00
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// Debug information queries.
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2006-04-07 16:34:46 +00:00
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unsigned getRARegister() const;
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2006-03-28 13:48:33 +00:00
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unsigned getFrameRegister(MachineFunction &MF) const;
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2008-02-02 00:17:00 +00:00
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int getFrameIndexOffset(MachineFunction &MF, int FI) const;
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2007-01-24 19:15:24 +00:00
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void getInitialFrameState(std::vector<MachineMove> &Moves) const;
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2007-02-21 22:54:50 +00:00
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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2002-10-25 22:55:53 +00:00
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};
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2006-05-05 05:40:20 +00:00
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// getX86SubSuperRegister - X86 utility function. It returns the sub or super
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// register of a specific X86 register.
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// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
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unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false);
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2003-11-11 22:41:34 +00:00
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} // End llvm namespace
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2002-10-25 22:55:53 +00:00
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#endif
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