2011-08-16 21:11:21 +00:00
|
|
|
@ RUN: not llvm-mc -triple=thumbv6-apple-darwin < %s 2> %t
|
|
|
|
@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
|
2011-08-19 20:46:54 +00:00
|
|
|
@ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t
|
|
|
|
@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s
|
2013-09-05 14:14:19 +00:00
|
|
|
@ RUN: not llvm-mc -triple=thumbv8 < %s 2> %t
|
|
|
|
@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s
|
2011-08-16 21:11:21 +00:00
|
|
|
|
|
|
|
@ Check for various assembly diagnostic messages on invalid input.
|
|
|
|
|
|
|
|
@ ADD instruction w/o 'S' suffix.
|
|
|
|
add r1, r2, r3
|
|
|
|
@ CHECK-ERRORS: error: invalid instruction
|
|
|
|
@ CHECK-ERRORS: add r1, r2, r3
|
|
|
|
@ CHECK-ERRORS: ^
|
2011-08-16 22:20:01 +00:00
|
|
|
|
|
|
|
@ Instructions which require v6+ for both registers to be low regs.
|
|
|
|
add r2, r3
|
|
|
|
mov r2, r3
|
|
|
|
@ CHECK-ERRORS: error: instruction variant requires Thumb2
|
|
|
|
@ CHECK-ERRORS: add r2, r3
|
|
|
|
@ CHECK-ERRORS: ^
|
2011-08-19 20:46:54 +00:00
|
|
|
@ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later
|
|
|
|
@ CHECK-ERRORS-V5: mov r2, r3
|
|
|
|
@ CHECK-ERRORS-V5: ^
|
2011-08-17 22:49:09 +00:00
|
|
|
|
|
|
|
|
|
|
|
@ Out of range immediates for ASR instruction.
|
|
|
|
asrs r2, r3, #33
|
|
|
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
|
|
|
@ CHECK-ERRORS: asrs r2, r3, #33
|
|
|
|
@ CHECK-ERRORS: ^
|
2011-08-17 23:11:13 +00:00
|
|
|
|
|
|
|
@ Out of range immediates for BKPT instruction.
|
|
|
|
bkpt #256
|
|
|
|
bkpt #-1
|
|
|
|
error: invalid operand for instruction
|
|
|
|
bkpt #256
|
|
|
|
^
|
|
|
|
error: invalid operand for instruction
|
|
|
|
bkpt #-1
|
|
|
|
^
|
2011-08-18 21:50:53 +00:00
|
|
|
|
2013-09-05 14:14:19 +00:00
|
|
|
@ Out of range immediates for v8 HLT instruction.
|
|
|
|
hlt #64
|
|
|
|
hlt #-1
|
|
|
|
@CHECK-ERRORS: error: instruction requires: armv8 arm-mode
|
|
|
|
@CHECK-ERRORS: hlt #64
|
|
|
|
@CHECK-ERRORS: ^
|
|
|
|
@CHECK-ERRORS-V8: error: instruction requires: arm-mode
|
|
|
|
@CHECK-ERRORS-V8: hlt #64
|
|
|
|
@CHECK-ERRORS-V8: ^
|
|
|
|
@CHECK-ERRORS: error: invalid operand for instruction
|
|
|
|
@CHECK-ERRORS: hlt #-1
|
|
|
|
@CHECK-ERRORS: ^
|
|
|
|
|
2011-08-18 21:50:53 +00:00
|
|
|
@ Invalid writeback and register lists for LDM
|
|
|
|
ldm r2!, {r5, r8}
|
|
|
|
ldm r2, {r5, r7}
|
2011-08-22 23:01:07 +00:00
|
|
|
ldm r2!, {r2, r3, r4}
|
2013-10-22 19:00:39 +00:00
|
|
|
ldm r2!, {r2, r3, r4, r10}
|
|
|
|
ldmdb r2!, {r2, r3, r4}
|
2011-08-18 21:50:53 +00:00
|
|
|
@ CHECK-ERRORS: error: registers must be in range r0-r7
|
|
|
|
@ CHECK-ERRORS: ldm r2!, {r5, r8}
|
|
|
|
@ CHECK-ERRORS: ^
|
|
|
|
@ CHECK-ERRORS: error: writeback operator '!' expected
|
|
|
|
@ CHECK-ERRORS: ldm r2, {r5, r7}
|
|
|
|
@ CHECK-ERRORS: ^
|
2011-08-22 23:01:07 +00:00
|
|
|
@ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
|
2011-08-22 23:04:26 +00:00
|
|
|
@ CHECK-ERRORS: ldm r2!, {r2, r3, r4}
|
2011-08-22 23:01:07 +00:00
|
|
|
@ CHECK-ERRORS: ^
|
2013-10-22 19:00:39 +00:00
|
|
|
@ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
|
|
|
|
@ CHECK-ERRORS-V8: ldm r2!, {r2, r3, r4, r10}
|
|
|
|
@ CHECK-ERRORS-V8: ^
|
2013-10-24 09:37:18 +00:00
|
|
|
@ CHECK-ERRORS-V8: error: writeback register not allowed in register list
|
2013-10-22 19:00:39 +00:00
|
|
|
@ CHECK-ERRORS-V8: ldmdb r2!, {r2, r3, r4}
|
|
|
|
@ CHECK-ERRORS-V8: ^
|
2011-08-19 19:29:25 +00:00
|
|
|
|
2011-08-22 23:17:34 +00:00
|
|
|
@ Invalid writeback and register lists for PUSH/POP
|
|
|
|
pop {r1, r2, r10}
|
|
|
|
push {r8, r9}
|
|
|
|
@ CHECK-ERRORS: error: registers must be in range r0-r7 or pc
|
|
|
|
@ CHECK-ERRORS: pop {r1, r2, r10}
|
|
|
|
@ CHECK-ERRORS: ^
|
|
|
|
@ CHECK-ERRORS: error: registers must be in range r0-r7 or lr
|
|
|
|
@ CHECK-ERRORS: push {r8, r9}
|
|
|
|
@ CHECK-ERRORS: ^
|
|
|
|
|
|
|
|
|
2011-08-23 18:15:37 +00:00
|
|
|
@ Invalid writeback and register lists for STM
|
|
|
|
stm r1, {r2, r6}
|
|
|
|
stm r1!, {r2, r9}
|
2013-10-22 19:00:39 +00:00
|
|
|
stm r2!, {r2, r9}
|
|
|
|
stmdb r2!, {r0, r2}
|
2012-04-24 22:40:08 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: thumb2
|
2011-08-23 18:15:37 +00:00
|
|
|
@ CHECK-ERRORS: stm r1, {r2, r6}
|
|
|
|
@ CHECK-ERRORS: ^
|
|
|
|
@ CHECK-ERRORS: error: registers must be in range r0-r7
|
|
|
|
@ CHECK-ERRORS: stm r1!, {r2, r9}
|
|
|
|
@ CHECK-ERRORS: ^
|
2013-10-22 19:00:39 +00:00
|
|
|
@ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
|
|
|
|
@ CHECK-ERRORS-V8: stm r2!, {r2, r9}
|
|
|
|
@ CHECK-ERRORS-V8: ^
|
2013-10-24 09:37:18 +00:00
|
|
|
@ CHECK-ERRORS-V8: error: writeback register not allowed in register list
|
2013-10-22 19:00:39 +00:00
|
|
|
@ CHECK-ERRORS-V8: stmdb r2!, {r0, r2}
|
|
|
|
@ CHECK-ERRORS-V8: ^
|
2011-08-22 23:17:34 +00:00
|
|
|
|
2011-08-19 19:29:25 +00:00
|
|
|
@ Out of range immediates for LSL instruction.
|
|
|
|
lsls r4, r5, #-1
|
|
|
|
lsls r4, r5, #32
|
|
|
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
|
|
|
@ CHECK-ERRORS: lsls r4, r5, #-1
|
|
|
|
@ CHECK-ERRORS: ^
|
|
|
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
|
|
|
@ CHECK-ERRORS: lsls r4, r5, #32
|
|
|
|
@ CHECK-ERRORS: ^
|
2011-08-19 22:07:46 +00:00
|
|
|
|
|
|
|
@ Mismatched source/destination operands for MUL instruction.
|
|
|
|
muls r1, r2, r3
|
2011-08-19 22:30:46 +00:00
|
|
|
@ CHECK-ERRORS: error: destination register must match source register
|
2011-08-19 22:07:46 +00:00
|
|
|
@ CHECK-ERRORS: muls r1, r2, r3
|
|
|
|
@ CHECK-ERRORS: ^
|
2011-08-23 18:33:38 +00:00
|
|
|
|
|
|
|
|
|
|
|
@ Out of range immediates for STR instruction.
|
|
|
|
str r2, [r7, #-1]
|
|
|
|
str r5, [r1, #3]
|
|
|
|
str r3, [r7, #128]
|
2012-04-24 22:40:08 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: thumb2
|
2011-08-23 18:33:38 +00:00
|
|
|
@ CHECK-ERRORS: str r2, [r7, #-1]
|
|
|
|
@ CHECK-ERRORS: ^
|
2012-04-24 22:40:08 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: thumb2
|
2011-08-23 18:33:38 +00:00
|
|
|
@ CHECK-ERRORS: str r5, [r1, #3]
|
|
|
|
@ CHECK-ERRORS: ^
|
2012-04-24 22:40:08 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: thumb2
|
2011-08-23 18:33:38 +00:00
|
|
|
@ CHECK-ERRORS: str r3, [r7, #128]
|
|
|
|
@ CHECK-ERRORS: ^
|
2011-08-23 19:49:10 +00:00
|
|
|
|
|
|
|
@ Out of range immediate for SVC instruction.
|
|
|
|
svc #-1
|
|
|
|
svc #256
|
|
|
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
|
|
|
@ CHECK-ERRORS: svc #-1
|
|
|
|
@ CHECK-ERRORS: ^
|
2012-04-24 22:40:08 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: arm-mode
|
2011-08-23 19:49:10 +00:00
|
|
|
@ CHECK-ERRORS: svc #256
|
|
|
|
@ CHECK-ERRORS: ^
|
2011-08-24 21:22:15 +00:00
|
|
|
|
|
|
|
|
|
|
|
@ Out of range immediate for ADD SP instructions
|
|
|
|
add sp, #-1
|
|
|
|
add sp, #3
|
|
|
|
add sp, sp, #512
|
|
|
|
add r2, sp, #1024
|
2012-04-24 22:40:08 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: thumb2
|
2011-08-24 21:22:15 +00:00
|
|
|
@ CHECK-ERRORS: add sp, #-1
|
|
|
|
@ CHECK-ERRORS: ^
|
2012-04-24 22:40:08 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: thumb2
|
2011-08-24 21:22:15 +00:00
|
|
|
@ CHECK-ERRORS: add sp, #3
|
|
|
|
@ CHECK-ERRORS: ^
|
2012-04-24 22:40:08 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: thumb2
|
2011-08-24 21:22:15 +00:00
|
|
|
@ CHECK-ERRORS: add sp, sp, #512
|
|
|
|
@ CHECK-ERRORS: ^
|
2012-04-24 22:40:08 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: arm-mode
|
2011-08-24 21:22:15 +00:00
|
|
|
@ CHECK-ERRORS: add r2, sp, #1024
|
2011-09-01 00:28:52 +00:00
|
|
|
@ CHECK-ERRORS: ^
|
2012-04-27 23:51:36 +00:00
|
|
|
|
|
|
|
add r2, sp, ip
|
|
|
|
@ CHECK-ERRORS: error: source register must be the same as destination
|
|
|
|
@ CHECK-ERRORS: add r2, sp, ip
|
|
|
|
@ CHECK-ERRORS: ^
|
2013-08-09 10:38:32 +00:00
|
|
|
|
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
2013-08-15 15:43:06 +00:00
|
|
|
@ B/Bcc - out of range immediates for Thumb1 branches
|
2013-08-09 10:38:32 +00:00
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
beq #-258
|
|
|
|
bne #256
|
|
|
|
bgt #13
|
|
|
|
b #-1048578
|
|
|
|
b #1048576
|
|
|
|
b #10323
|
|
|
|
|
2013-09-30 18:50:51 +00:00
|
|
|
@ CHECK-ERRORS: error: branch target out of range
|
|
|
|
@ CHECK-ERRORS: error: branch target out of range
|
|
|
|
@ CHECK-ERRORS: error: branch target out of range
|
|
|
|
@ CHECK-ERRORS: error: branch target out of range
|
|
|
|
@ CHECK-ERRORS: error: branch target out of range
|
|
|
|
@ CHECK-ERRORS: error: branch target out of range
|
2013-08-09 10:38:32 +00:00
|
|
|
|
2012-05-02 09:43:18 +00:00
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
@ WFE/WFI/YIELD - are not supported pre v6T2
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
wfe
|
|
|
|
wfi
|
|
|
|
yield
|
|
|
|
|
2013-10-07 11:10:47 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
|
2012-05-02 09:43:18 +00:00
|
|
|
@ CHECK-ERRORS: wfe
|
|
|
|
@ CHECK-ERRORS: ^
|
2013-10-07 11:10:47 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
|
2012-05-02 09:43:18 +00:00
|
|
|
@ CHECK-ERRORS: wfi
|
|
|
|
@ CHECK-ERRORS: ^
|
2013-10-07 11:10:47 +00:00
|
|
|
@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
|
2012-05-02 09:43:18 +00:00
|
|
|
@ CHECK-ERRORS: yield
|
|
|
|
@ CHECK-ERRORS: ^
|
|
|
|
|
2013-08-06 16:07:46 +00:00
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
@ PLDW required mp-extensions
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
pldw [r0, #4]
|
|
|
|
@ CHECK-ERRORS: error: instruction requires: mp-extensions
|
2013-08-15 15:43:06 +00:00
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
@ LDR(lit) - invalid offsets
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
ldr r4, [pc, #-12]
|
|
|
|
@ CHECK-ERRORS: error: instruction requires: thumb2
|
|
|
|
|
2014-08-05 14:58:05 +00:00
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
@ STC2{L}/LDC2{L} - requires thumb2
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
stc2 p0, c8, [r1, #4]
|
|
|
|
stc2l p6, c2, [r7, #4]
|
|
|
|
ldc2 p0, c8, [r1, #4]
|
|
|
|
ldc2l p6, c2, [r7, #4]
|
|
|
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
|
|
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
|
|
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
|
|
|
@ CHECK-ERRORS: error: invalid operand for instruction
|