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https://github.com/c64scene-ar/llvm-6502.git
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minor renaming
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25640 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -90,7 +90,7 @@ class BFormD<bits<6> opcode, string asmstr, list<dag> pattern>
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let Inst{20-0} = disp;
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}
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let isBranch = 1, isTerminator = 1 in
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class BFormDG<bits<6> opcode, string asmstr, list<dag> pattern>
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class BForm<bits<6> opcode, string asmstr, list<dag> pattern>
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: InstAlpha<opcode, (ops GPRC:$RA, target:$DISP), asmstr> {
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let Pattern = pattern;
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@ -764,21 +764,21 @@ let Ra = 31 in
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def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)]>;
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//Branches, int
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def BEQ : BFormDG<0x39, "beq $RA,$DISP",
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[(brcond (seteq GPRC:$RA, 0), bb:$DISP)]>;
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def BGE : BFormDG<0x3E, "bge $RA,$DISP",
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[(brcond (setge GPRC:$RA, 0), bb:$DISP)]>;
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def BGT : BFormDG<0x3F, "bgt $RA,$DISP",
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[(brcond (setgt GPRC:$RA, 0), bb:$DISP)]>;
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def BLBC : BFormDG<0x38, "blbc $RA,$DISP", []>; //TODO: Low bit clear
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def BLBS : BFormDG<0x3C, "blbs $RA,$DISP",
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[(brcond (and GPRC:$RA, 1), bb:$DISP)]>;
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def BLE : BFormDG<0x3B, "ble $RA,$DISP",
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[(brcond (setle GPRC:$RA, 0), bb:$DISP)]>;
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def BLT : BFormDG<0x3A, "blt $RA,$DISP",
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[(brcond (setlt GPRC:$RA, 0), bb:$DISP)]>;
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def BNE : BFormDG<0x3D, "bne $RA,$DISP",
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[(brcond (setne GPRC:$RA, 0), bb:$DISP)]>;
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def BEQ : BForm<0x39, "beq $RA,$DISP",
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[(brcond (seteq GPRC:$RA, 0), bb:$DISP)]>;
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def BGE : BForm<0x3E, "bge $RA,$DISP",
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[(brcond (setge GPRC:$RA, 0), bb:$DISP)]>;
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def BGT : BForm<0x3F, "bgt $RA,$DISP",
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[(brcond (setgt GPRC:$RA, 0), bb:$DISP)]>;
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def BLBC : BForm<0x38, "blbc $RA,$DISP", []>; //TODO: Low bit clear
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def BLBS : BForm<0x3C, "blbs $RA,$DISP",
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[(brcond (and GPRC:$RA, 1), bb:$DISP)]>;
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def BLE : BForm<0x3B, "ble $RA,$DISP",
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[(brcond (setle GPRC:$RA, 0), bb:$DISP)]>;
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def BLT : BForm<0x3A, "blt $RA,$DISP",
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[(brcond (setlt GPRC:$RA, 0), bb:$DISP)]>;
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def BNE : BForm<0x3D, "bne $RA,$DISP",
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[(brcond (setne GPRC:$RA, 0), bb:$DISP)]>;
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//Branches, float
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def FBEQ : FBForm<0x31, "fbeq $RA,$DISP",
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