Commit Graph

120193 Commits

Author SHA1 Message Date
Alexey Samsonov
d33a944a7d Updating branches/google/testing to r243773
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/google/testing@243815 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-01 00:04:09 +00:00
JF Bastien
48db91bcc3 x86: check hasOpaqueSPAdjustment in canRealignStack
Summary:
@rnk pointed out in [1] that x86's canRealignStack logic should match that in CantUseSP from hasBasePointer.

  [1]: http://reviews.llvm.org/D11160?id=29713#inline-89350

Reviewers: rnk

Subscribers: rnk, llvm-commits

Differential Revision: http://reviews.llvm.org/D11377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243772 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 18:28:09 +00:00
JF Bastien
6877df25a0 WebAssembly: handle unused function arguments.
Subscribers: llvm-commits, sunfish, jfb

Differential Revision: http://reviews.llvm.org/D11684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243770 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 18:13:27 +00:00
David Majnemer
4c43d5bdfa Attempt to appease the MSVC build bots
They don't seem to care for initializing an ArrayRef with a
std::initializer_list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243769 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 18:13:25 +00:00
Kostya Serebryany
207cfe14a9 [libFuzzer] record traces from the switch statements only when told to do so
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243768 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 18:09:08 +00:00
David Majnemer
4a45f0871a New EH representation for MSVC compatibility
This introduces new instructions neccessary to implement MSVC-compatible
exception handling support.  Most of the middle-end and none of the
back-end haven't been audited or updated to take them into account.

Differential Revision: http://reviews.llvm.org/D11097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243766 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 17:58:14 +00:00
Duncan P. N. Exon Smith
aa50fa7c2f DI: Rewrite the DIBuilder local variable API
Replace the general `createLocalVariable()` with two more specific
functions: `createParameterVariable()` and `createAutoVariable()`, and
rewrite the documentation.

Besides cleaning up the API, this avoids exposing the fake DWARF tags
`DW_TAG_arg_variable` and `DW_TAG_auto_variable` to frontends, and is
preparation for removing them completely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243764 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 17:55:53 +00:00
JF Bastien
3f2cb5c959 WebAssembly: print basic integer assembly.
Summary:
This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats:

  - The operation names are currently incorrect.
  - Other integer and floating-point types will be added later.
  - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways.
  - The assembly format isn't full s-expressions yet either, this will be added later.
  - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter).

Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243763 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 17:53:38 +00:00
David Majnemer
0229c3b7ad [COFF] Consider the ImageBase when reporting section addresses
This lets us reenable the lld test disabled in r243758.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243761 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 17:40:24 +00:00
Kostya Serebryany
26e09e2da5 [libFuzzer] support switch interception in dfsan mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243760 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 17:05:05 +00:00
Benjamin Kramer
3973e4b71b [CodeGenPrepare] Compress a pair. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243759 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 17:00:39 +00:00
Sanjay Patel
8ae0800ae1 [x86] reassociate integer multiplies using machine combiner pass
Add i16, i32, i64 imul machine instructions to the list of reassociation
candidates.

A new bit of logic is needed to handle integer instructions: they have an
implicit EFLAGS operand, so we have to make sure it's dead in order to do
any reassociation with integer ops.

Differential Revision: http://reviews.llvm.org/D11660



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243756 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 16:21:55 +00:00
Reid Kleckner
c136e5507a [COFF] Return symbol VAs instead of RVAs for PE files
This makes llvm-nm consistent with binutils nm on executables and DLLs.
For a vanilla hello world executable, the address of main should include
the default image base of 0x400000.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243755 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 16:14:22 +00:00
Geoff Berry
0dd663b598 [AArch64] Favor extended reg patterns for sub
Summary:
Favor the extended reg patterns over the shifted reg patterns that match
only the operand shift and not the full sign/zero extend and shift.

Reviewers: jmolloy, t.p.northover

Subscribers: mcrosier, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D11569

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243753 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 15:55:54 +00:00
Sanjay Patel
29b8ad6749 don't repeat function names in comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243751 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 15:10:44 +00:00
Bruno Cardoso Lopes
8fea35acad [CaptureTracker] Provide an ordered basic block to PointerMayBeCapturedBefore
This patch is a follow up from r240560 and is a step further into
mitigating the compile time performance issues in CaptureTracker.

By providing the CaptureTracker with a "cached ordered basic block"
instead of computing it every time, MemDepAnalysis can use this cache
throughout its calls to AA->callCapturesBefore, avoiding to recompute it
for every scanned instruction. In the same testcase used in r240560,
compile time is reduced from 2min to 30s.

This also fixes PR22348.

rdar://problem/19230319
Differential Revision: http://reviews.llvm.org/D11364

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243750 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 14:31:35 +00:00
Daniel Sanders
289b5e7f39 [regalloc] Make RegMask clobbers prevent merging vreg's into PhysRegs when hoisting def's upwards.
Summary:
This prevents vreg260 and D7 from being merged in:
  %vreg260<def> = LDC1 ...
  JAL <ga:@sin>, <regmask ... list not containing D7 ...>
  %D7<def> = COPY %vreg260; ...
Doing so is not valid because the JAL clobbers the D7.

This fixes the almabench regression in the LLVM 3.7.0 release branch.

Reviewers: MatzeB

Subscribers: MatzeB, qcolombet, hans, llvm-commits

Differential Revision: http://reviews.llvm.org/D11649


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243745 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 12:58:55 +00:00
Jingyue Wu
c71235ab7d Refactor: Simplify boolean conditional return statements in lib/Target/NVPTX
Summary: Use clang-tidy to simplify boolean conditional return statements

Reviewers: rafael, echristo, chandlerc, bkramer, craig.topper, dexonsmith, chapuni, eliben, jingyue, jholewinski

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D9983

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243734 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 05:09:47 +00:00
Matt Arsenault
30eac4b85a AMDGPU: Fix v16i32 to v16i8 truncstore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243731 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 04:12:04 +00:00
Kostya Serebryany
02c18f4db9 [libFuzzer] trace switch statements and apply mutations based on the expected case values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243726 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 01:33:06 +00:00
Tom Stellard
8cb3db9e93 ELFYAML: Enable parsing of EM_AMDGPU
Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11263

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243724 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 01:15:15 +00:00
Matt Arsenault
01e2215a94 AMDGPU/SI: Set DwarfRegNum
This requires a fix in tablegen for the cast<int> from bits<16>
to work in the list initializer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243723 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 01:12:10 +00:00
Matt Arsenault
6a224c30a5 TableGen: Support folding casts from bits to int
This is to fix an incorrect error when trying to initialize
DwarfNumbers with a !cast<int> of a bits initializer.
getValuesAsListOfInts("DwarfNumbers") would not see an IntInit
and instead the cast, so would give up.

It seems likely that this could be generalized to attempt
the convertInitializerTo for any type. I'm not really sure
why the existing code seems to special case the string cast cases
when convertInitializerTo seems like it should generally handle this
sort of thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243722 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 01:12:06 +00:00
Tom Stellard
a29a752cf5 docs: Add information about helper scripts to HowToReleaseLLVM page
Differential Revision: http://reviews.llvm.org/D10081

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243720 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 01:02:35 +00:00
Tom Stellard
b0619e0be3 AMDGPU/SI: Remove unused pattern for f32 constant loads
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11603

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243719 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 01:02:32 +00:00
Sumanth Gundapaneni
8d13756ddd [ARM] Lower modulo operation to generate __aeabi_divmod on Android
For a modulo (reminder) operation,
clang -target armv7-none-linux-gnueabi generates "__modsi3"
clang -target armv7-none-eabi generates "__aeabi_idivmod"
clang -target armv7-linux-androideabi generates "__modsi3"
Android bionic libc doesn't provide a __modsi3, instead it provides a
"__aeabi_idivmod". This patch fixes the LLVM ARMISelLowering to generate
the correct call when ever there is a modulo operation.

Differential Revision: http://reviews.llvm.org/D11661


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243717 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 00:45:12 +00:00
Alex Lorenz
2623dd4454 MIR Parser: Report an error when a constant pool item is redefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243696 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 22:00:17 +00:00
Alex Lorenz
2bc631660b MIR Parser: Report an error when a virtual register is redefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 21:54:10 +00:00
Sanjay Patel
8a6197a968 fix memcpy/memset/memmove lowering when optimizing for size
Fixing MinSize attribute handling was discussed in D11363. 
This is a prerequisite patch to doing that.

The handling of OptSize when lowering mem* functions was broken
on Darwin because it wants to ignore -Os for these cases, but the
existing logic also made it ignore -Oz (MinSize).

The Linux change demonstrates a widespread problem. The backend
doesn't usually recognize the MinSize attribute by itself; it
assumes that if the MinSize attribute exists, then the OptSize 
attribute must also exist. 

Fixing this more generally will be a follow-on patch or two.

Differential Revision: http://reviews.llvm.org/D11568



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243693 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 21:41:50 +00:00
Kostya Serebryany
dd6dcb6cee [libFuzzer] fix the strncmp interceptor -- it should respect short strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243691 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 21:22:22 +00:00
Eric Christopher
f4745ecbb4 Fix TableGen code generation for ReadNone attribute.
Patch by Pete Abred!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243689 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 21:16:34 +00:00
Sanjay Patel
3b00227629 enable fast-math-flag propagation to DAG nodes
This uncovered latent bugs previously:
http://reviews.llvm.org/D10403

...but it's time to try again because internal tests aren't finding more.

If time passes and no other bugs are reported, we can remove this cl::opt.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243687 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 21:06:55 +00:00
Adhemerval Zanella
044eeda22c Enable dfsan for aarch64
This patch enable DFSan memory transformation for aarch64 (39-bit VMA).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243684 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 20:49:35 +00:00
Mehdi Amini
93204d28b8 Add a TargetMachine hook that verifies DataLayout compatibility
Summary: Also provide the associated assertion when CodeGen starts.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11654

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243682 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 20:33:18 +00:00
Wei Mi
4db6728b3a [SLP vectorizer]: Choose the best consecutive candidate to pair with a store instruction.
The patch changes the SLPVectorizer::vectorizeStores to choose the immediate
succeeding or preceding candidate for a store instruction when it has multiple
consecutive candidates. In this way it has better chance to find more slp
vectorization opportunities.

Differential Revision: http://reviews.llvm.org/D10445


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243666 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 17:40:39 +00:00
Mehdi Amini
778e06475b Fix lli with OrcLazyJIT: the default DataLayout was used.
Set the correct one using the TargetMachine instead.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243664 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 17:29:33 +00:00
Matt Arsenault
ece90bb19e AMDGPU: Set SubRegIndex size and offset
I'm not sure what reasons the comment here could have
had for not setting these. Without these set, there is
an assertion hit during DWARF emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243661 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 17:03:11 +00:00
Matt Arsenault
b240003d58 AMDGPU: Fix unreachable when emitting binary debug info
Copy implementation of applyFixup from AArch64 with AArch64 bits
ripped out.

Tests will be included with a later commit. Several other
problems must be fixed before binary debug info emission
will work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243660 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 17:03:08 +00:00
Alex Lorenz
fbd94791e6 MIR Serialization: Serialize the machine basic block's successor weights.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243659 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 16:54:38 +00:00
David Majnemer
cfe562c99b [COFF] Add IMAGE_SCN_TYPE_NOLOAD to SectionCharacteristics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243658 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 16:47:56 +00:00
Tom Stellard
a495784ea0 AMDGPU/SI: Simplify moveSMRDToVALU()
Summary:
Replace the switch on instruction opcode with a switch on register size.
This way we don't need to update the switch statement when we add new
SMRD variants.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11601

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243652 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 16:20:42 +00:00
Tom Stellard
a3a8dc4c30 AMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfo
Summary:
This function is never called.  isReallyTriviallyReMaterializable() is
the function that should be implemented instead.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11620

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243651 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 16:20:40 +00:00
Vasileios Kalintiris
f04b7c7d06 [mips] Fix out-of-date debug information in test file.
Update the debug info in the check-lines because the change in r243638
introduced a constant initialization before the prologue's end as part
of a register spill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243640 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 13:13:09 +00:00
NAKAMURA Takumi
fc77c83c74 MCJITTests/MCJITCAPITest.cpp: Try to appease i686-win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243639 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 13:06:53 +00:00
Vasileios Kalintiris
458b5f3d9b [mips][FastISel] Remove hidden mips-fast-isel option.
Summary:
This hidden option would disable code generation through FastISel by
default. It was removed from the available options and from the
Fast-ISel tests that required it in order to run the tests.

Reviewers: dsanders

Subscribers: qcolombet, llvm-commits

Differential Revision: http://reviews.llvm.org/D11610

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243638 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 12:39:33 +00:00
Vasileios Kalintiris
3b79f0ccc3 [mips][FastISel] Apply only zero-extension to constants prior to their materialization.
Summary:
Previously, we would sign-extend non-boolean negative constants and
zero-extend otherwise. This was problematic for PHI instructions with
negative values that had a type with bitwidth less than that of the
register used for materialization.

More specifically, ComputePHILiveOutRegInfo() assumes the constants
present in a PHI node are zero extended in their container and
afterwards deduces the known bits.

For example, previously we would materialize an i16 -4 with the
following instruction:

  addiu $r, $zero, -4

The register would end-up with the 32-bit 2's complement representation
of -4. However, ComputePHILiveOutRegInfo() would generate a constant
with the upper 16-bits set to zero. The SelectionDAG builder would use
that information to generate an AssertZero node that would remove any
subsequent trunc & zero_extend nodes.

In theory, we should modify ComputePHILiveOutRegInfo() to consult
target-specific hooks about the way they prefer to materialize the
given constants. However, git-blame reports that this specific code
has not been touched since 2011 and it seems to be working well for every
target so far.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11592

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243636 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 11:51:44 +00:00
Daniel Sanders
4b26be6066 [test-release.sh] Add -no-libunwind to disable it on targets that don't support it.
Summary:
Mips doesn't implement unw_getcontext() or libunwind::Registers_*::jumpto() yet
so we must disable libunwind for this release.

Reviewers: hans

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11563

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243633 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 10:14:57 +00:00
Michael Kuperstein
78a589c319 [X86] Recognize "flags" as an identifier, not a register in Intel-syntax inline asm
Patch by: marina.yatsina@intel.com
Differential Revision: http://reviews.llvm.org/D11512


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243630 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 10:10:25 +00:00
Matt Arsenault
d8c145fd49 Add amdopencl environment to triple
This is used by the AMD x86 OpenCL implementation
to change some ABI details on Windows and Linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243627 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 08:16:51 +00:00
Adam Nemet
77907c7555 [LoopVer] Add missing std::move
The reason I was passing this vector by value in the constructor so that
I wouldn't have to copy when initializing the corresponding member but
then I forgot the std::move.

The use-case is LoopDistribution which filters the checks then
std::moves it to LoopVersioning's constructor.  With this interface we
can avoid any copies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243616 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 04:21:13 +00:00