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036c6e877b
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9542 Commits

Author SHA1 Message Date
Andrew Trick
036c6e877b Add missing HasAVX512 predicate. 
This was only working because AVX had cheaper rules in all cases.
I'm sure there are other places in this file where predicates are missing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192276 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 05:11:10 +00:00
Craig Topper
0c73c428d9 Replace a couple instructions with patterns referring to other instructions with same encoding and operands. Mark a couple other instructions as CodeGenOnly since we have FR and VR instructions and only one of them is needed by the assembler/disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192274 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 04:54:21 +00:00
Craig Topper
28ffa8a643 Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB prefix and keeps the mnemonic from starting with an extra 'v' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192272 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 04:24:38 +00:00
Craig Topper
442b23a817 Mark some instructions as CodeGenOnly since they aren't needed by the assembler or disassembler. Disassembler already filtered them, but asm parser still had them in its tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192271 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 03:56:16 +00:00
Craig Topper
b96a393b09 Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192266 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 02:18:34 +00:00
Rafael Espindola
320296a4cf Add a MCTargetStreamer interface. 
This patch fixes an old FIXME by creating a MCTargetStreamer interface
and moving the target specific functions for ARM, Mips and PPC to it.

The ARM streamer is still declared in a common place because it is
used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are
completely hidden in the corresponding Target directories.

I will send an email to llvmdev with instructions on how to use this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 13:08:17 +00:00
Craig Topper
d55fed16a4 Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192175 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 06:30:39 +00:00
Craig Topper
b9bc43852c Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 05:53:50 +00:00
Benjamin Kramer
51a8280fbb X86: Fix type check. Just because an integer type is illegal doesn't mean it's i64. 
Fixes PR17495, where an i24 triggered this code. It's intended to
optimize i64 loads on 32 bit x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192123 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 19:11:35 +00:00
Rafael Espindola
ef8c4ca252 Remove getEHExceptionRegister and getEHHandlerRegister. 
They haven't been used for a long time. Patch by MathOnNapkins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192099 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 13:39:22 +00:00
Craig Topper
e778f82a1e Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 07:19:47 +00:00
Craig Topper
510fb362a8 Remove FsMOVAPSrr and friends. They have no patterns and are no longer selected anywhere. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192089 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 06:10:45 +00:00
Craig Topper
8fdba75d5b Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. 
This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192088 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 05:42:48 +00:00
Craig Topper
36a9b31b98 Add disassembler support for long encodings for INC/DEC in 32-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 04:28:06 +00:00
Benjamin Kramer
d9f7a185e3 X86: Don't fold spills into SSE operations if the stack is unaligned. 
Regalloc can emit unaligned spills nowadays, but we can't fold the
spills into SSE ops if we can't guarantee alignment. PR12250.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192064 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-06 13:48:22 +00:00
Elena Demikhovsky
714319a169 AVX-512: added scalar convert instructions and intrinsics. 
Fixed load folding in VPERM2I instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-06 13:11:09 +00:00
Elena Demikhovsky
a6269ee5fb AVX-512: fixed shuffle lowering 
in case of BLEND and added VSHUFPS patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192055 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-06 06:11:18 +00:00
Craig Topper
984fbe6c65 Add TBM instructions to loading folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192046 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-05 20:20:51 +00:00
Nick Lewycky
e66dd40d74 Rename this feature to "cx16" to match gcc's flag name. Apparently these strings 
are directly tied to the flag names in clang with no remapping in between?


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192044 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-05 20:11:44 +00:00
Craig Topper
617ba175da Remove underscores from TBM instruction names for consistency with other instruction naming. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192040 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-05 19:27:26 +00:00
Craig Topper
22abf7e17f Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192039 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-05 19:22:59 +00:00
Craig Topper
e2522fd06c Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192037 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-05 17:17:53 +00:00
Elena Demikhovsky
5086ff1320 AVX-512: Fixed encoding of VMOVQ instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191889 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 12:03:26 +00:00
Craig Topper
198f1b340a Replace C++ style comment with a C style comment to satisfy some of the build bots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191880 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 06:29:59 +00:00
Craig Topper
e3b0a9c51a Remove comma from the end of an enum. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191877 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 06:18:26 +00:00
Craig Topper
279d28265d Add XOP disassembler support. Fixes PR13933. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 05:17:48 +00:00
Craig Topper
fafe4bbd6c Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 04:16:45 +00:00
Elena Demikhovsky
c699417f11 AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 target 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191818 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-02 12:20:42 +00:00
Elena Demikhovsky
d243c19c1f AVX-512: Added TB prefix to all instructions without prefixes, 
otherwise encoding fails after the last change in X86MCCodeEmitter.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191812 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-02 06:39:07 +00:00
Rafael Espindola
8819c84aed Remove several unused variables. 
Patch by Alp Toker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191757 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 13:32:03 +00:00
Elena Demikhovsky
c8d0d00781 AVX-512: Added X86vzmovl patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191733 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 08:38:02 +00:00
Craig Topper
18a8e10720 Remove 0 as a valid encoding for the m-mmmm field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191732 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 07:10:28 +00:00
Craig Topper
8568510d46 Remove unneeded fields from disassembler internal instruction format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191731 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 06:56:57 +00:00
Craig Topper
f99f63db79 BEXTR should be defined to take same type for bother operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191728 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 03:48:26 +00:00
Preston Gurd
7813a2fe9d Forgot to add a break statement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191715 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 23:51:22 +00:00
Preston Gurd
2967a80412 The X86FixupLEAs pass for Intel Atom must not call convertToThreeAddress 
on ADD16rr opcodes, if src1 != src, since that would cause 
convertToThreeAddress to try to create a virtual register. This is not
permitted after register allocation, which is when the X86FixupLEAs pass
runs.

This patch fixes PR16785.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191711 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 23:18:42 +00:00
Craig Topper
92b4581953 Various x86 disassembler fixes. 
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191649 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 02:46:36 +00:00
Craig Topper
f63c806e11 Change type of XOP flag in code emitters to a bool. Remove a some unneeded cases from switch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191632 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-29 08:33:34 +00:00
Craig Topper
bd0decae3c Add comments for XOPA map introduced with TBM instructions.a 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191630 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-29 06:31:18 +00:00
Robert Wilhelm
f80a63fa23 Fix spelling intruction -> instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191610 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-28 11:46:15 +00:00
Yunzhong Gao
685707c28e Adding intrinsics to the llvm backend for TBM instruction set. 
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-27 18:38:42 +00:00
Craig Topper
62f6fac1c5 Put HasAVX512 predicate on some patterns to properly disable them when AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191490 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-27 07:20:47 +00:00
Craig Topper
1f31a3794e Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS is used in AVX512 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191489 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-27 07:16:24 +00:00
Craig Topper
11989c2685 Removal some duplicate patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191488 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-27 07:11:17 +00:00
Yunzhong Gao
d7f5fac111 Fixing Intel format of the vshufpd instruction. 
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191481 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-27 01:44:23 +00:00
Andrew Trick
0701564377 Mark the x86 machine model as incomplete. PR17367. 
Ideally, the machinel model is added at the time the instructions are
defined. But many instructions in X86InstrSSE.td still need a model.

Without this workaround the scheduler asserts because x86 already has
itinerary classes for these instructions, indicating they should be
modeled by the scheduler. Since we use the new machine model for other
instructions, it expects a new machine model for these too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191391 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-25 18:14:12 +00:00
David Majnemer
8ba3f9c900 MC: Remove vestigial PCSymbol field from AsmInfo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191362 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-25 09:36:11 +00:00
Yunzhong Gao
4da61345ec Adding a feature flag to the llvm backend for x86 TBM instruction set. 
Adding TBM feature to bdver2 processor; piledriver supports this instruction set
according to the following document:
http://developer.amd.com/wordpress/media/2012/10/New-Bulldozer-and-Piledriver-Instructions.pdf

Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1692



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191324 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-24 18:21:52 +00:00
Bill Wendling
42d4259524 Followup to r191252. 
Make sure that the code that handles the constant addresses is run for the
GEPs. This just refactors that code and then calls it for the GEPs that are
collected during the iteration.

<rdar://problem/12445434>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191281 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-24 07:19:30 +00:00
Bill Wendling
cb3023ae51 Selecting the address from a very long chain of GEPs can blow the stack. 
The recursive nature of the address selection code can cause the stack to
explode if there is a long chain of GEPs. Convert the recursive bit into a
iterative method to avoid this.

<rdar://problem/12445434>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191252 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-24 00:13:08 +00:00