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1674 Commits

Author SHA1 Message Date
Bill Wendling
af56634058 Reapply r79127. It was fixed by d0k. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-15 21:21:19 +00:00
Bill Wendling
f865ea85bd Revert r79127. It was causing compilation errors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-15 21:14:01 +00:00
Evan Cheng
088880cb19 Change allowsUnalignedMemoryAccesses to take type argument since some targets 
support unaligned mem access only for certain types. (Should it be size
instead?)

ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79127 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-15 19:23:44 +00:00
Evan Cheng
bc9b754091 Turn on if-conversion for thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-15 07:59:10 +00:00
Evan Cheng
010b1b9e7b Do not use frame register to reference fixed stack objects if the function is frameless. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79067 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-15 02:05:35 +00:00
Evan Cheng
98a0104014 Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79039 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 20:48:13 +00:00
Anton Korobeynikov
72977a45a8 Allow targets to specify their choice of calling conventions per 
libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.

Patch by Sandeep!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79033 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 20:10:52 +00:00
Evan Cheng
e6c835f424 Add Thumb2 lsr hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79032 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 20:09:37 +00:00
Evan Cheng
59bc0604e5 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79026 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 19:11:20 +00:00
Evan Cheng
bba9f5f378 Indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79022 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 19:01:37 +00:00
Evan Cheng
31b99dd760 Also shrink immediate branches; also more assembler workarounds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79014 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 18:31:44 +00:00
Bob Wilson
22cac0d9b3 Now that all the legal Neon shuffles (or at least the ones that have been 
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78995 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 05:16:33 +00:00
Bob Wilson
c1d287b4b7 Create a new ARM-specific DAG node, VDUP, to represent a splat from a 
scalar_to_vector.  Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78994 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 05:13:08 +00:00
Bob Wilson
0ce3710825 During legalization, change Neon vdup_lane operations from shuffles to 
target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78993 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 05:08:32 +00:00
Evan Cheng
a1efbbdbf3 Shrink ADR and LDR from constantpool late during constantpool island pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78970 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 00:32:16 +00:00
Evan Cheng
1135a232eb New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78968 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 00:16:47 +00:00
Owen Anderson
1d0be15f89 Push LLVMContexts through the IntegerType APIs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 21:58:54 +00:00
Daniel Dunbar
b42dad4761 Revert 78892 and 78895, these break generating working executables on 
x86_64-apple-darwin10.

--- Reverse-merging r78895 into '.':
U    test/CodeGen/PowerPC/2008-12-12-EH.ll
U    lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U    include/llvm/Target/DarwinTargetAsmInfo.h
U    lib/Target/X86/X86TargetAsmInfo.cpp
U    lib/Target/X86/X86TargetAsmInfo.h
U    lib/Target/ARM/ARMTargetAsmInfo.h
U    lib/Target/ARM/ARMTargetMachine.cpp
U    lib/Target/ARM/ARMTargetAsmInfo.cpp
U    lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U    lib/Target/PowerPC/PPCTargetAsmInfo.h
U    lib/Target/PowerPC/PPCTargetMachine.cpp
G    lib/Target/DarwinTargetAsmInfo.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 17:03:38 +00:00
Jim Grosbach
f35d21617e Add missing defs of R2 and D1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78918 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 16:59:44 +00:00
David Goodwin
6d3d9c3fc3 Finalize itineraries for cortex-a8 integer multiply 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 15:51:13 +00:00
Jim Grosbach
8db5cce021 Remove unnecessary newline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78905 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 15:12:16 +00:00
Jim Grosbach
1add659b0a Correct comment wording 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78904 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 15:11:43 +00:00
Evan Cheng
48bd7e3bbc tPOP_RET now has predicate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78898 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 06:05:07 +00:00
Bob Wilson
bfcbb507c2 Add a fixme message about canonicalizing floating-point vector types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78897 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 06:01:30 +00:00
Bob Wilson
bab812b4b0 Revert r78852 for now. I want to do this differently, but I don't have time 
to fix it tonight.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78896 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 05:58:56 +00:00
Evan Cheng
86e5f7b6f8 It's ok to spill a tGPR register as long as it's still allocated a low register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78893 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 05:40:51 +00:00
Chris Lattner
b2d3169d96 fix a minor fixme. When building with SL and later tools, the ".eh" symbols 
don't need to be exported from the .o files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78892 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 05:30:22 +00:00
Bruno Cardoso Lopes
b808588a3a Change MCSectionELF to represent a section semantically instead of 
syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78890 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 05:07:35 +00:00
Bob Wilson
28865062c1 Add a comment to describe why vector shuffles are legalized to custom DAG nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78884 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 02:13:04 +00:00
Bob Wilson
d06791f6d0 Use cast<> instead of dyn_cast<> in places where the type is known. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78881 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 01:57:47 +00:00
Dan Gohman
cf20ac4fd1 Various AsmWriter output cleanups. Use WriteAsOperand instead of 
PrintUnmangledNameSafely.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78878 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 01:36:44 +00:00
Bob Wilson
af385baa1d Recognize Neon VDUP shuffles during legalization instead of selection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78852 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 22:54:19 +00:00
Bob Wilson
d8e1757eac Recognize Neon VREV shuffles during legalization instead of selection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 22:31:50 +00:00
Dan Gohman
a9ad04191c This void is implicit in C++. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78848 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 22:10:57 +00:00
Bob Wilson
114a266c94 Generate Neon VTBL and VTBX instructions from the corresponding intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78835 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 20:51:55 +00:00
Evan Cheng
3aaccffbce PredCC is meant to be 2 bits wide, like PredCC1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78829 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 18:35:50 +00:00
David Goodwin
1a8f36e3ce Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78827 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 18:31:53 +00:00
Jim Grosbach
bff392384d Add catch block handling to SjLj exception handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78817 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 17:38:44 +00:00
Bob Wilson
9f7d60f460 Fix TableGen warnings. This partly reverts my previous change to this file, 
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78815 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 17:04:56 +00:00
Jim Grosbach
378756c0f2 register naming cleanup (s/ip/r12/) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78806 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 15:21:13 +00:00
Chris Lattner
a7ac47cee1 Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple 
pair instead of from a virtual method on TargetMachine.  This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use 
TargetAsmInfo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78802 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 07:22:17 +00:00
Evan Cheng
007ea274f4 Shrink Thumb2 movcc instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78790 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 05:17:19 +00:00
Evan Cheng
e0d7fe8550 Remove another Darwin assembler workaround. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78779 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 02:07:19 +00:00
Evan Cheng
c972165b11 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78778 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 02:03:03 +00:00
Evan Cheng
ea253b99e9 Remove an Darwin assembler workaround. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78777 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 01:56:42 +00:00
Evan Cheng
05c269c645 Shrink ADDS, ADC, RSB, and SUBS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78776 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 01:49:45 +00:00
Bob Wilson
dbd3c0e06d Add missing chain operands for VLD* and VST* instructions. 
Set "mayLoad" and "mayStore" on the load/store instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78761 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 00:49:01 +00:00
Evan Cheng
b89030ab65 Shrinkify Thumb2 r = add sp, imm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78745 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 23:00:31 +00:00
Chris Lattner
e2b060161c Change the asmprinter to print the comment character before the 
"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character.  This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character.  This also allows hoisting the darwin stuff up to the
shared TAI class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78737 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 22:39:40 +00:00
David Goodwin
546952fd60 Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78736 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 22:38:43 +00:00