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Author SHA1 Message Date
Joey Gouly
4cbbbf49b6 This reverts r155000. 
The cdp2 instruction should have the same restrictions as cdp on the
co-processor registers.

VFP instructions on v8/AArch32 share the same encoding space as cdp2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184445 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 17:42:36 +00:00
Nadav Rotem
d69d9f20bc SLPVectorization: Add a basic support for cross-basic block slp vectorization. 
We collect gather sequences when we vectorize basic blocks. Gather sequences are excellent
hints for vectorization of other basic blocks.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184444 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 17:41:45 +00:00
David Blaikie
63b8e299e4 Give this X86-specific test a triple so it's actually X86-specific. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184443 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 17:31:32 +00:00
Ulrich Weigand
151ad37fed [MC] Support @ variants with directional labels 
The assembler parser common code supports recognizing symbol variants
using the @ modifer.  On PowerPC, it should also be possible to use
(some of) those modifiers with directional labels, like "1f@l".

This patch adds support for accepting symbol variants on directional
labels as well.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184437 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 16:24:17 +00:00
Ulrich Weigand
027e94479c [PowerPC] Optimize @ha/@l constructs 
This patch adds support for having the assembler optimize fixups
to constructs like "symbol@ha" or "symbol@l" if "symbol" can be
resolved at assembler time.

This optimization is already present in the PPCMCExpr.cpp code
for handling PPC_HA16/PPC_LO16 target expressions.  However,
those target expression were used only on Darwin targets.

This patch changes target expression code so that they are
usable also with the GNU assembler (using the @ha / @l syntax
instead of the ha16() / lo16() syntax), and changes the
MCInst lowering code to generate those target expressions
where appropriate.

It also changes the asm parser to generate HA16/LO16 target
expressions when parsing assembler source that uses the
@ha / @l modifiers.  The effect is that now the above-
mentioned optimization automatically becomes available
for those situations too.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184436 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 16:23:52 +00:00
Ulrich Weigand
0db5379fe6 [PowerPC] Support compare mnemonics with implied CR0 
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).

This patch adds support for those extended compare mnemonics.


Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
 
 # CHECK: cmpdi 2, 3, 128                 # encoding: [0x2d,0x23,0x00,0x80]
          cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128                 # encoding: [0x2c,0x23,0x00,0x80]
+         cmpdi 3, 128
 # CHECK: cmpd 2, 3, 4                    # encoding: [0x7d,0x23,0x20,0x00]
          cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4                    # encoding: [0x7c,0x23,0x20,0x00]
+         cmpd 3, 4
 # CHECK: cmpldi 2, 3, 128                # encoding: [0x29,0x23,0x00,0x80]
          cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128                # encoding: [0x28,0x23,0x00,0x80]
+         cmpldi 3, 128
 # CHECK: cmpld 2, 3, 4                   # encoding: [0x7d,0x23,0x20,0x40]
          cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4                   # encoding: [0x7c,0x23,0x20,0x40]
+         cmpld 3, 4
 
 # CHECK: cmpwi 2, 3, 128                 # encoding: [0x2d,0x03,0x00,0x80]
          cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128                 # encoding: [0x2c,0x03,0x00,0x80]
+         cmpwi 3, 128
 # CHECK: cmpw 2, 3, 4                    # encoding: [0x7d,0x03,0x20,0x00]
          cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4                    # encoding: [0x7c,0x03,0x20,0x00]
+         cmpw 3, 4
 # CHECK: cmplwi 2, 3, 128                # encoding: [0x29,0x03,0x00,0x80]
          cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128                # encoding: [0x28,0x03,0x00,0x80]
+         cmplwi 3, 128
 # CHECK: cmplw 2, 3, 4                   # encoding: [0x7d,0x03,0x20,0x40]
          cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4                   # encoding: [0x7c,0x03,0x20,0x40]
+         cmplw 3, 4
 
 # FIXME: Trap mnemonics
 
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
 defm : BranchExtendedMnemonic<"nu", 100>;
 defm : BranchExtendedMnemonic<"ns", 100>;
 
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 16:15:12 +00:00
Rafael Espindola
440dfe9644 Make sure ar is creating a new file instead of updating an existing one. 
Should fix the bots that are seeing a corrupted file from a previous run.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184424 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 13:44:49 +00:00
Rafael Espindola
122c57c0b8 Add r184420 back, but also handle long file names. 
Original message:

Don't include directory names in archives.

This matches the behavior of both gnu and os x versions of ar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184423 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 13:41:51 +00:00
Rafael Espindola
9d39cb1d64 Revert "Don't include directory names in archives." 
This reverts commit 184420.
Investigating the bot failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184421 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 13:23:48 +00:00
Rafael Espindola
be984d6376 Don't include directory names in archives. 
This matches the behavior of both gnu and os x versions of ar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184420 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 13:16:44 +00:00
Vladimir Medic
7231625f75 Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184411 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 11:21:49 +00:00
David Blaikie
4532c280f5 DebugInfo: don't use location lists when the location covers the whole function anyway 
Fix up three tests - one that was relying on abbreviation number,
another relying on a location list in this case (& testing raw asm,
changed that to use dwarfdump on the debug_info now that that's where
the location is), and another which was added in r184368 - exposing a
bug in that fix that is exposed when we emit the location inline rather
than through a location list. Fix that bug while I'm here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184387 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 00:25:24 +00:00
David Blaikie
cc631588a9 Spelling correction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184370 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 22:00:13 +00:00
David Blaikie
0159ae4295 DebugInfo: PR14763/r183329 correct the location of indirect parameters 
We had been papering over a problem with location info for non-trivial
types passed by value by emitting their type as references (this caused
the debugger to interpret the location information correctly, but broke
the type of the function). r183329 corrected the type information but
lead to the debugger interpreting the pointer parameter as the value -
the debug info describing the location needed an extra dereference.

Use a new flag in DIVariable to add the extra indirection (either by
promoting an existing DW_OP_reg (parameter passed in a register) to
DW_OP_breg + 0 or by adding DW_OP_deref to an existing DW_OP_breg + n
(parameter passed on the stack).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184368 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 21:55:13 +00:00
David Blaikie
0812304ad8 Spell correct (s/begining/beginning/) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184362 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 21:42:05 +00:00
David Blaikie
3df7d2f70b llvm-dwarfdump: Add support for dumping the .debug_loc section 
This is a basic implementation - we still don't have any support (that I
know of) for dumping DWARF expressions in a meaningful way, so the
location information itself is just printed as a sequence of bytes as we
do elsewhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 21:37:13 +00:00
Ulrich Weigand
4df4bccc71 [MC/DWARF] Generate multiple .debug_line entries for adjacent .loc directives 
The compiler occasionally generates multiple .loc directives in a row
(at the same instruction address).  These need to be transformed into
multple actual .debug_line table entries, since they are used to signal
certain information to the debugger (e.g. if the opening brace of a
function body is on the same line as the declaration).

The MCAsmStreamer version of EmitDwarfLocDirective handles this
correctly by emitting a .loc directive every time it is called.
However, the MCObjectStream version simply defaults to recording
the information and emitting only a single table entry later,
e.g. when EmitInstruction is called.

This patch introduces a MCAsmStreamer::EmitDwarfLocDirective
version that emits a line table entry for a .loc directive
that may already be pending before recording the new directive.
(This is similar to how this is handled in GNU as.)

With this patch (and the code alignment factor patch) applied,
I'm now getting identical DWARF .debug sections for all test-suite
object files on PowerPC for the internal and the external assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184357 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 21:27:27 +00:00
Matt Arsenault
ad966ea7a8 Move StructurizeCFG out of R600 to generic Transforms. 
Register it with PassManager

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184343 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 20:18:24 +00:00
Quentin Colombet
5a2fb058d3 LSR: Fix the parameters used to compute the scaling factor cost. 
Prior to this change, the considered addressing modes may be invalid since the
maximum and minimum offsets were not taking into account.
This was causing an assertion failure.

The added test case exercices that behavior.

<rdar://problem/14199725> Assertion failed: (CurScaleCost >= 0 && "Legal
addressing mode has an illegal cost!")


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184341 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 19:59:41 +00:00
Nadav Rotem
80a6d6526c SLPVectorizer: handle scalars that are extracted from vectors (using ExtractElementInst). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184325 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 17:33:16 +00:00
Nadav Rotem
7d180ac7b6 SLPVectorizer: start constructing chains at stores that are not power of two. 
The type <3 x i8> is a common in graphics and we want to be able to vectorize it.

This changes accelerates bullet by 12% and 471_omnetpp by 5%.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184317 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 15:57:29 +00:00
Rafael Espindola
8fe960ed50 Remove the 'R' modifier. 
It is not present in GNU or OS X versions and doesn't make a lot of sense
for llvm-ar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184306 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 14:58:16 +00:00
Nadav Rotem
eb30e5115e SLPVectorizer: vectorize compares and selects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184282 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 05:49:52 +00:00
Sean Silva
6e6259d105 [yaml2obj][ELF] Beef up this test a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184269 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 00:55:32 +00:00
Sean Silva
ea94e114b4 [yaml2obj][ELF] Support ELFOSABI_* enum. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184268 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 00:55:28 +00:00
Sean Silva
5ba1225fb0 [yaml2obj][ELF] Support st_info through Binding and Type YAML keys. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184263 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 00:11:59 +00:00
Sean Silva
ca0170ffa1 [yaml2obj][ELF] Ensure STN_UNDEF entry is present. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184258 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 23:19:17 +00:00
Sean Silva
afcf60fe15 [yaml2obj][ELF] Rudimentary symbol table support. 
Currently, we only output the name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184255 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 23:14:03 +00:00
Jim Grosbach
a95e3091eb ARM: Add optional datatype suffix to NEON mvn asm syntax. 
rdar://14194152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184244 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 21:49:21 +00:00
Tim Northover
c4cc006a09 AArch64: remove accidental test output file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184236 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 21:16:53 +00:00
Kevin Enderby
bf811d602d Change the arm assembler to support this from the v7c spec: 
"When assembling to the ARM instruction set, the .N qualifier produces
an assembler error and the .W qualifier has no effect."

In the pre-matcher handler in the asm parser the ".w" (wide) qualifier 
when in ARM mode is now discarded. And an error message is now
produced when the ".n" (narrow) qualifier is used in ARM mode.

Test cases for these were added.

rdar://14064574


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184224 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 20:19:24 +00:00
Quentin Colombet
a3fb49cd85 During SelectionDAG building explicitly set a node to constant zero when the 
value is zero.
This allows optmizations to kick in more easily.
Fix some test cases so that they remain meaningful (i.e., not completely dead
coded) when optimizations apply.

<rdar://problem/14096009> superfluous multiply by high part of zero-extended
value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184222 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 20:14:39 +00:00
Jack Carter
571dd98ea4 Mips ELF: Mark object file as ABI compliant 
When producing objects that are abi compliant we are 
marking neither the object file nor the assembly file
correctly and thus generate warnings. 

We need to set the EF_CPIC flag in the ELF header when
generating direct object.

Note that the warning is only generated when compiling without PIC.

When compiling with clang the warning will be suppressed by supplying:

 -Wa,-mno-shared -Wa,-call_nonpic

Also the following directive should also be added:

	.option	pic0

when compiling without PIC,  This eliminates the need for supplying:

  -mno-shared -call_nonpic

on the assembler command line.

Patch by Douglas Gilmore


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184220 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 19:47:15 +00:00
Stefanus Du Toit
23306deb92 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes. 
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184207 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 17:08:10 +00:00
Alexey Samsonov
9c22f87b13 Basic support for parsing Mach-O universal binaries in LLVMObject library 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184191 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 15:03:28 +00:00
Amaury de la Vieuville
beb920fce6 ARM: fix literal load with positive offset encoding 
When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly

This patch also makes the assembler look at the .w/.n specifier for
loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 08:13:05 +00:00
Amaury de la Vieuville
f8b60d6f30 ARM: add operands pre-writeback variants when needed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184181 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 08:12:51 +00:00
Amaury de la Vieuville
ce046b98ed ARM: fix thumb literal loads decoding 
This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184180 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 08:03:06 +00:00
Amaury de la Vieuville
cea0032f73 ARM: thumb stores cannot use PC as dest register 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184179 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 08:02:56 +00:00
Andrew Trick
ad626132a9 Reenable, improve, and add MI-Sched unit tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184134 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-17 21:45:16 +00:00
Vincent Lejeune
f7c9b95f94 R600: PV stores Reg id, not index 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184117 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-17 20:16:40 +00:00
Vincent Lejeune
98f5cf8000 R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen. 
Fixes rv7x0 bug in Heaven reported here:
https://bugs.freedesktop.org/show_bug.cgi?id=64257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184116 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-17 20:16:26 +00:00
Benjamin Kramer
4eed756153 Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 
The main advantages here are way better heuristics, taking into account not
just loop depth but also __builtin_expect and other static heuristics and will
eventually learn how to use profile info. Most of the work in this patch is
pushing the MachineBlockFrequencyInfo analysis into the right places.

This is good for a 5% speedup on zlib's deflate (x86_64), there were some very
unfortunate spilling decisions in its hottest loop in longest_match(). Other
benchmarks I tried were mostly neutral.

This changes register allocation in subtle ways, update the tests for it.
2012-02-20-MachineCPBug.ll was deleted as it's very fragile and the instruction
it looked for was gone already (but the FileCheck pattern picked up unrelated
stuff).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184105 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-17 19:00:36 +00:00
Pekka Jaaskelainen
a8a04380c5 Fix for a regression caused by the LoopVectorizer when 
vectorizing loops with memory accesses to non-zero address spaces. It
simply dropped the AS info. Fixes PR16306.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184103 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-17 18:49:06 +00:00
Rafael Espindola
b6a633ca94 Add a testcase for r184074. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184080 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-17 14:00:41 +00:00
Tim Northover
7338de37a8 AArch64: print relocation addends if present on AArch64 
llvm-objdump should provide some way of printing out the addends present in the
.rela sections for debugging purposes if nothing else.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184072 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-17 03:03:06 +00:00
David Blaikie
6d9dbd5526 Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions 
Rather than using the full power of target-specific addressing modes in
DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This
reduces the complexity of debug info handling down to two
representations of values (reg+offset and frame index+offset) rather
than three or four.

Ideally we could ensure that frame indicies had been eliminated by the
time we reached an assembly or dwarf generation, but I haven't spent the
time to figure out where the FIs are leaking through into that & whether
there's a good place to convert them. Some FI+offset=>reg+offset
conversion is done (see PrologEpilogInserter, for example) which is
necessary for some SelectionDAG assumptions about registers, I believe,
but it might be possible to make this a more thorough conversion &
ensure there are no remaining FIs no matter how instruction selection
is performed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184066 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-16 20:34:15 +00:00
David Blaikie
4bb23594f3 DebugInfo: follow up to 184045 to constrain the tests further to ensure they don't contain +0 offsets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184046 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-15 16:02:44 +00:00
David Blaikie
f14b44c71b DebugInfo: print DBG_VALUE MachineInstrs with [] for deref and drop the offset when it's zero 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184045 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-15 15:52:58 +00:00
Andrew Trick
b86a0cdb67 Machine Model: Add MicroOpBufferSize and resource BufferSize. 
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-15 04:49:57 +00:00