Evan Cheng
4b322e58b7
Shrinkify Thumb2 load / store multiple instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 21:11:32 +00:00
Owen Anderson
825b72b057
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
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the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 20:47:22 +00:00
Owen Anderson
e50ed30282
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:56:29 +00:00
Evan Cheng
e8af1f9afe
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 02:37:24 +00:00
Anton Korobeynikov
8e9ece75db
Use subclassing to print lane-like immediates (w/o hash) eliminating
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'no_hash' modifier. Hopefully this will make Daniel happy :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 23:10:41 +00:00
Evan Cheng
57834cdee5
tADDhirr should target GPR, not tGPR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78454 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 03:19:44 +00:00
Evan Cheng
53c67c0218
tBfar is bl, which clobbers LR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78370 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 05:45:07 +00:00
Evan Cheng
861986401e
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 00:34:42 +00:00
David Goodwin
8b7d7ade85
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 16:52:47 +00:00
Evan Cheng
35d6c41fde
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 23:47:55 +00:00
Evan Cheng
b620724e61
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
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instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-01 00:16:10 +00:00
Evan Cheng
20a2a0aff3
Make sure Thumb2 uses the right call instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 21:26:42 +00:00
Evan Cheng
0531d04d00
- Fix an obvious copy and paste error.
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- Darwin Thumb2 call clobbers r9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77500 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 20:10:36 +00:00
Evan Cheng
e7c329bf4b
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28 20:53:24 +00:00
David Goodwin
c9d138f505
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77242 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27 19:59:26 +00:00
Evan Cheng
d83360694a
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77172 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-26 23:59:01 +00:00
Evan Cheng
81c102ba66
Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
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Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76889 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-23 18:26:03 +00:00
Evan Cheng
eadf04992a
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22 22:03:29 +00:00
Evan Cheng
756da12ae4
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76729 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22 06:46:53 +00:00
Evan Cheng
4a8b7d030b
Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22 06:37:28 +00:00
Evan Cheng
3ecadc816d
Do not select tSXTB / tSXTH in thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-21 18:15:26 +00:00
Evan Cheng
a6e4322ccc
Fix tSUBspi operand definition. It reads and writes sp, which is a high register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76155 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-17 05:43:12 +00:00
Evan Cheng
f6bc4ae4a1
1. In Thumb mode, select tBx instead of ARM variants.
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2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75585 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-14 01:49:27 +00:00
Evan Cheng
2f297df02e
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75360 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-11 07:08:13 +00:00
Evan Cheng
446c428bf3
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
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A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-11 06:43:01 +00:00
Evan Cheng
892837abf3
We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75219 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 02:09:04 +00:00
Evan Cheng
06e16587eb
Add a thumb2 pass to insert IT blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 01:54:42 +00:00
Evan Cheng
e5564748b7
Added Thumb IT instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75198 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-09 23:43:36 +00:00
David Goodwin
f1daf7d8ab
Use common code for both ARM and Thumb-2 instruction and register info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 23:10:31 +00:00
David Goodwin
334c26473b
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 16:09:28 +00:00
David Goodwin
5e47a9a6e4
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74543 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 18:04:13 +00:00
Evan Cheng
f3c21b857b
A few more load instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 02:15:48 +00:00
David Goodwin
c0309b48b5
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 15:33:01 +00:00
Evan Cheng
055b0310f8
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 07:51:04 +00:00
Evan Cheng
9cb9e6778c
Renaming for consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74368 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 02:26:13 +00:00
Evan Cheng
e864b74e95
tst is also commutable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74236 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 00:19:07 +00:00
David Goodwin
c9ee1189c5
Add Def/Use of CPSR for Thumb-1 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74219 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 22:49:55 +00:00
David Goodwin
9a36bdbaf1
Test commit
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74185 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 17:52:32 +00:00
Evan Cheng
7dcf4a826c
Some reorg and additional comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74152 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 01:05:06 +00:00
Evan Cheng
a09b9ca10f
Add Thumb2 pc relative add.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74141 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 23:47:58 +00:00
Evan Cheng
09c39fcf83
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73985 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 19:38:13 +00:00
Bob Wilson
1c76d0ee5c
Add explicit types for shift count constants. This is in preparation for
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another change that makes the types ambiguous (at least as far as tablegen
is concerned).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73909 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22 22:08:29 +00:00
Eli Friedman
6b7bb42c36
Mark a few Thumb instructions commutable; just happened to spot this
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while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73746 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 01:43:08 +00:00
Evan Cheng
cd799b99cb
Mark some pattern-less instructions as neverHasSideEffects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 20:46:18 +00:00
Jim Grosbach
c93f961874
correct register class for tADDspi to GPR since the register will always be SP
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71602 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-12 22:30:18 +00:00
Jim Grosbach
30eae3c022
PR2985 / <rdar://problem/6584986>
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When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07 20:34:09 +00:00
Jim Grosbach
0ede14f5c0
remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67874 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-27 23:06:27 +00:00
Dan Gohman
15511cf166
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 18:15:48 +00:00
Dan Gohman
f5aeb1a8e4
Rename ConstantSDNode::getValue to getZExtValue, for consistency
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with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-12 16:56:44 +00:00
Evan Cheng
130966411f
More refactoring.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 06:41:12 +00:00