Commit Graph

32217 Commits

Author SHA1 Message Date
David Blaikie
0cb00dbc56 Matching ARM change for r227481: DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227488 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 20:23:47 +00:00
Matt Arsenault
fa711758df R600/SI: Implement enableAggressiveFMAFusion
Add tests for the various combines. This should
always be at least cycle neutral on all subtargets for f64,
and faster on some. For f32 we should prefer selecting
v_mad_f32 over v_fma_f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227484 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 19:34:32 +00:00
Matt Arsenault
c416d94735 R600/SI: Add subtarget feature for if f32 fma is fast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227483 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 19:34:25 +00:00
Matt Arsenault
30a5d21457 R600/SI: Fix tonga's basic scheduling model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227482 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 19:34:18 +00:00
David Blaikie
1ba26f8da1 DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumps
The use of the DbgLoc in FastISel is probably something we should fix.
It's prone to leaking the wrong location into instructions - we should
have a clear chain of custody from the debug location of an IR
Instruction to that of a MachineInstr to avoid such leakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227481 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 19:09:18 +00:00
Rafael Espindola
9936b80df5 Compute the ELF SectionKind from the flags.
Any code creating an MCSectionELF knows ELF and already provides the flags.

SectionKind is an abstraction used by common code that uses a plain
MCSection.

Use the flags to compute the SectionKind. This removes a lot of
guessing and boilerplate from the MCSectionELF construction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227476 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 17:33:21 +00:00
Colin LeMahieu
dec5091220 [Hexagon] Deleting old variants of intrinsics and adding missing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227474 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 17:26:56 +00:00
Colin LeMahieu
f1b4917f1b [Hexagon] Adding CR intrinsic tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227463 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 16:55:37 +00:00
Tom Stellard
882d1b71e0 R600/SI: Remove stray debug statements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227462 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 16:55:28 +00:00
Tom Stellard
51a3c27d6e R600/SI: Define a schedule model and enable the generic machine scheduler
The schedule model is not complete yet, and could be improved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227461 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 16:55:25 +00:00
Colin LeMahieu
48a3c8261f [Hexagon] Deleting unused classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227460 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 16:35:38 +00:00
Robert Lougher
1031549bec [X86] Use single add/sub for large stack offsets
For large stack offsets the compiler generates multiple immediate mode
sub/add instructions in the prologue/epilogue.  This patch makes the
compiler place the final amount to be added/subtracted into a register,
which is then added/substracted with a single operation.

Differential Revision: http://reviews.llvm.org/D7226


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227458 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 16:18:29 +00:00
Colin LeMahieu
c7260e2ffa [Hexagon] Adding XTYPE/PRED intrinsic tests. Converting predicate types to i32 instead of i1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227457 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 16:08:43 +00:00
Bill Schmidt
a5ea0b50a4 [PowerPC] Complete setting the baseline for ppc64le
Patch by Nemanja Ivanovic.

As was uncovered by the failing test case (when run on non-PPC
platforms), the feature set when compiling with -march=ppc64le was not
being picked up. This change ensures that if the -mcpu option is not
specified, the correct feature set is picked up regardless of whether
we are on PPC or not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227455 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 15:59:09 +00:00
Rafael Espindola
248a6cf2c0 Remove MergeableConst.
Only the specific ones (MergeableConst4, MergeableConst8, MergeableConst16) are
handled specially.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227440 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 14:12:41 +00:00
Vladimir Medic
d0fb85865a [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227430 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 11:33:41 +00:00
Eric Christopher
bd2a700208 Remove getSubtargetImpl from AArch64ISelLowering and cache the
correct subtarget by passing it in during the constructor as
TargetLowering is Subtarget specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227402 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 00:19:42 +00:00
Eric Christopher
3dd7e82123 Remove getSubtargetImpl from ARMISelLowering and cache the
correct subtarget by passing it in during the constructor as
TargetLowering is Subtarget specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227401 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 00:19:39 +00:00
Eric Christopher
92185fdb9f Small cleanup in ARMFastISel initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227400 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 00:19:37 +00:00
Eric Christopher
a6deca3e1b Migrate ARM except for TTI, AsmPrinter, and frame lowering
away from getSubtargetImpl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227399 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29 00:19:33 +00:00
Sanjay Patel
d5502c5f13 fix typos; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227386 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 22:37:32 +00:00
Colin LeMahieu
24373e35a4 [Hexagon] Updating several V5 intrinsics and adding FP tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227379 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 22:08:16 +00:00
Simon Pilgrim
d0e8688ebc Spelling fixes. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227376 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 22:03:52 +00:00
Simon Pilgrim
5d8772fef5 Line endings fix. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227374 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 21:56:52 +00:00
Zoran Jovanovic
7624914c14 [mips][microMIPS] Implement SWM and LWM aliases
Differential Revision: http://reviews.llvm.org/D5820


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227373 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 21:52:27 +00:00
Sanjay Patel
143826f71b invert check for less indentation; use local vars to reduce duplication; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227355 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 19:44:21 +00:00
Colin LeMahieu
795ab51720 [Hexagon] Updating many V4 intrinsic patterns. Adding missing instruction and deleting unused classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227353 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 19:39:09 +00:00
Colin LeMahieu
a5062b38a9 [Hexagon] Adding XTYPE/MPY intrinsic tests and some missing multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227347 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 19:16:17 +00:00
Colin LeMahieu
4925c39604 [Hexagon] Deleting a lot of old variants of intrinsics and updating references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227338 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 18:29:11 +00:00
Colin LeMahieu
1135b0df02 [Hexagon] Converting XTYPE/BIT intrinsic patterns and adding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227335 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 18:06:23 +00:00
Sanjay Patel
9598bbc542 use SDValue methods directly instead of getNode()->* ; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227334 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 18:01:31 +00:00
Colin LeMahieu
a5070baf7e [Hexagon] Replacing XTYPE/SHIFT intrinsic patternss. Adding tests and missing instructions with tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227330 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 17:37:59 +00:00
Jozef Kolek
a8c8e06c02 [mips][microMIPS] Implement LWGP instruction
Differential Revision: http://reviews.llvm.org/D6650


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227325 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 17:27:26 +00:00
Colin LeMahieu
4b032d5f15 [Hexagon] Replacing intrinsics for halfword adds and max/min word/dword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227322 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 17:06:40 +00:00
Michael Kuperstein
837fe4388b [x32] Change the condition from bitness to LP64 for TCRETURNdi64.
TCRETURNmi64, which was mistakenly changed in r227307 will wait for another day.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227317 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 16:11:35 +00:00
Tom Stellard
ff340f98e3 R600: Move DataLayout to AMDGPUTargetMachine
This is a follow up to r227113.

It is now required to use the amdgcn target for SI and newer GPUs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227316 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 16:04:26 +00:00
Tom Stellard
9813f8be5d R600: Use a Southern Islands GPU as the default for the amdgcn target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227314 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 15:38:42 +00:00
Michael Kuperstein
0906c8fc1c [X86] Reduce some 32-bit imuls into lea + shl
Reduce integer multiplication by a constant of the form k*2^c, where k is in {3,5,9} into a lea + shl. Previously it was only done for imulq on 64-bit platforms, but it makes sense for imull and 32-bit as well.

Differential Revision: http://reviews.llvm.org/D7196

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227308 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 14:08:22 +00:00
Michael Kuperstein
e5b95695ea [x32] Enable sibcall optimization on x32.
This includes two things:
1) Fix TCRETURNdi and TCRETURN64di patterns to check the right thing (LP64 as opposed to target bitness).
2) Allow LEA64_32 in MatchingStackOffset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227307 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 13:38:48 +00:00
Elena Demikhovsky
b9d3801cd2 AVX-512: Added FMA intrinsics with rounding mode
By Asaf Badouh and Elena Demikhovsky

Added special nodes for rounding: FMADD_RND, FMSUB_RND..
It will prevent merge between nodes with rounding and other standard nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227303 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 10:21:27 +00:00
Craig Topper
aef361807e [X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227302 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 10:09:56 +00:00
Craig Topper
f3a2214da8 [X86] Merge printSSECC and printAVXCC. They only differed by an assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227301 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 10:09:52 +00:00
Chandler Carruth
52334f2ad8 [LPM] Stop using the string based preservation API. It is an
abomination.

For starters, this API is incredibly slow. In order to lookup the name
of a pass it must take a memory fence to acquire a pointer to the
managed static pass registry, and then potentially acquire locks while
it consults this registry for information about what passes exist by
that name. This stops the world of LLVMs in your process no matter
how little they cared about the result.

To make this more joyful, you'll note that we are preserving many passes
which *do not exist* any more, or are not even analyses which one might
wish to have be preserved. This means we do all the work only to say
"nope" with no error to the user.

String-based APIs are a *bad idea*. String-based APIs that cannot
produce any meaningful error are an even worse idea. =/

I have a patch that simply removes this API completely, but I'm hesitant
to commit it as I don't really want to perniciously break out-of-tree
users of the old pass manager. I'd rather they just have to migrate to
the new one at some point. If others disagree and would like me to kill
it with fire, just say the word. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227294 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 04:57:56 +00:00
Eric Christopher
b99395a7f7 Migrate AArch64 except for TTI and AsmPrinter away from getSubtargetImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227293 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 03:51:33 +00:00
Alexey Samsonov
00b7a940e7 Revert "[x86] Combine x86mmx/i64 to v2i64 conversion to use scalar_to_vector"
This reverts commits r226953 and r226974.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227248 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 21:34:11 +00:00
Kai Nacke
47b633d4a5 [mips] Add range checks and transformation to octeon instructions in AsmParser.
This patch adds range checks to the immediate operands of octeon
instructions in the AsmParser. Like gas, it applies the following
transformations if the immediate is to large:

bbit0 $8, 42, foo => bbit032 $8, 10, foo
bbit1 $8, 46, foo => bbit132 $8, 14, foo
cins $8, $31, 32, 31 => cins32 $8, $31, 0, 31
exts $7, $4, 54, 9 => exts32 $7, $4, 22, 9

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D7080


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227225 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 19:11:28 +00:00
Marek Olsak
d922eb0be9 R600/SI: Fix MIN3/MAX3 on VI, define MED3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227213 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 17:25:15 +00:00
Marek Olsak
2ba0c13c26 R600/SI: Don't set patterns for chip-specific instructions while having pseudos
Only pseudos have patterns on them.

Also don't set the asm string for VINTRP_Pseudo. All pseudos should have empty
asm.

This matches what all other multiclasses do.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227212 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 17:25:11 +00:00
Marek Olsak
9f824da16d R600/SI: Add VI versions of LDS atomics
Each class is split into two: one adds let statements around non-pseudos,
and the other one specifies the parameters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227211 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 17:25:07 +00:00
Marek Olsak
37788ca85a R600/SI: Add VI versions of MUBUF atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227210 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 17:25:02 +00:00