Chris Lattner
10d7fa62ff
Allow targets to custom lower their own intrinsics if desired.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27146 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 09:12:51 +00:00
Chris Lattner
e16449bcd8
Update dependencies to reflect split of the Intrinsics.td file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27144 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 07:45:48 +00:00
Chris Lattner
b8a45c2798
Add all of the altivec comparison instructions. Add patterns for the
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non-predicate altivec compare intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27143 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 04:57:17 +00:00
Chris Lattner
5d72907e00
Add and 8/16-bit adds, add all integer subtracts, add saturating subtract
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intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27142 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:39:02 +00:00
Chris Lattner
e7d959c069
implement the vsldoi intrinsic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27139 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 00:41:48 +00:00
Chris Lattner
af9136bc0c
fix the pattern for vandc, it's NOT vnand
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27136 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 23:10:40 +00:00
Chris Lattner
6509ae859a
add patterns for VANDC/VNOR, implementing
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CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27135 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 23:05:29 +00:00
Chris Lattner
c8e2c5561c
Add some comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27133 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 23:00:56 +00:00
Chris Lattner
c985d828bc
add a vnot helper node for matching 'not' on vectors
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27132 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 23:00:08 +00:00
Chris Lattner
452e8354d5
Fix a bug in ISD::isBuildVectorAllOnesInteger that caused it to always return
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false
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27131 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 22:59:28 +00:00
Chris Lattner
61d4399dfc
Implement the ISD::isBuildVectorAllOnesInteger predicate
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27130 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 22:57:01 +00:00
Chris Lattner
6ea2dee6f6
Don't call SimplifyDemandedBits on vectors
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27128 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 22:19:00 +00:00
Chris Lattner
2430a5f0c7
Add some logical operations
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27127 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 22:16:05 +00:00
Chris Lattner
98509ef3c7
Don't crash on packed logical ops
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27125 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 21:58:26 +00:00
Chris Lattner
fdbc82a925
Teach BinaryOperator::createNot to work with packed integer types
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27124 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 21:54:21 +00:00
Jim Laskey
e481b94bd5
Cast instruction not inserted into basic block.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27122 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 18:40:47 +00:00
Evan Cheng
6e16ee5634
Added missing (any_extend (load ...)) patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27120 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 09:45:48 +00:00
Evan Cheng
c60bd97b94
Build arbitrary vector with more than 2 distinct scalar elements with a
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series of unpack and interleave ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27119 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 09:37:23 +00:00
Chris Lattner
984f38bf4f
implement a bunch of intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27118 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 08:01:02 +00:00
Chris Lattner
b22a04d881
Move all Altivec stuff out into a new PPCInstrAltivec.td file.
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Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27117 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 07:51:43 +00:00
Chris Lattner
8d052bc711
Add some basic patterns for other datatypes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27116 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 07:39:07 +00:00
Chris Lattner
150ffa7842
add all supported formats to the vector register file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27115 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 07:36:56 +00:00
Chris Lattner
5a2025465b
Add support for __builtin_altivec_vnmsubfp /vmaddfp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27112 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 07:05:55 +00:00
Chris Lattner
420736dc85
#include Intrinsics.h into all dag isels
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 06:47:10 +00:00
Chris Lattner
b847423fc6
Implement Intrinsic::getName
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27108 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 06:32:47 +00:00
Chris Lattner
9c61dcf1aa
Codegen things like:
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<int -1, int -1, int -1, int -1>
and
<int 65537, int 65537, int 65537, int 65537>
Using things like:
vspltisb v0, -1
and:
vspltish v0, 1
instead of using constant pool loads.
This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27106 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 06:12:06 +00:00
Evan Cheng
ecac9cb959
Added SSE cachebility ops
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27103 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 06:03:26 +00:00
Evan Cheng
cc4f047dca
Instruction encoding bug
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27102 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 06:00:03 +00:00
Chris Lattner
ea93f63964
Add new intrinsic node definitions for tblgen use
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27100 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 02:29:35 +00:00
Evan Cheng
7b1d34bc6c
Added 128-bit packed integer subtraction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27096 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 01:33:37 +00:00
Evan Cheng
3246e06f84
Added CVTTPS2PI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27095 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 01:31:59 +00:00
Evan Cheng
7dda4052f5
Added CVTSS2SI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27094 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 01:00:18 +00:00
Evan Cheng
bc4832bc64
Support for scalar to vector with zero extension.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27091 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 23:15:12 +00:00
Chris Lattner
7255a54561
fix inverted conditional
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27089 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 22:49:42 +00:00
Jim Laskey
ff70fe61ed
D'oh - should be even numbered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27088 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 22:48:02 +00:00
Evan Cheng
c653d48022
Added LDMXCSR
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27087 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 22:28:37 +00:00
Chris Lattner
ac53eadc29
plug the intrinsics into the patterns for movmsk*
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27083 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 21:49:18 +00:00
Jim Laskey
47622e3721
Add dwarf register numbering to register data.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 21:15:58 +00:00
Jim Laskey
8da17b242f
Add support for dwarf register numbering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27080 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 21:13:21 +00:00
Jim Laskey
5b4939907e
Hack no more.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27079 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 21:10:36 +00:00
Chris Lattner
057f09bc0b
add another note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27077 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 20:04:27 +00:00
Chris Lattner
e6cd96d467
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27076 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 19:59:17 +00:00
Chris Lattner
da10f19d5c
Shuffle some includes around
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27073 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 18:52:35 +00:00
Evan Cheng
73d7b6029a
Only to vector shuffle for {x,x,y,y} cases when SCALAR_TO_VECTOR is free.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27071 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 18:45:20 +00:00
Chris Lattner
da91bdcfb0
expose intrinsic info to the targets.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27070 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 18:44:11 +00:00
Chris Lattner
8edd11f33d
Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27069 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 18:24:43 +00:00
Chris Lattner
54e869e18c
Like the comment says, prefer to use the implicit add done by [r+r] addressing
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modes than emitting an explicit add and using a base of r0. This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27068 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 17:58:06 +00:00
Jim Laskey
0bd135db59
Fix indent.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27065 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 10:08:23 +00:00
Jim Laskey
98a6979b25
Clean up some commentary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27064 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 10:00:56 +00:00
Jim Laskey
0892cee81f
Rename for truth in advertising.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27063 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 09:50:27 +00:00