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Author SHA1 Message Date
Evan Cheng
1b32f22b0f More logical ops patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27257 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 07:33:32 +00:00
Evan Cheng
0876aa5178 Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27256 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 06:21:22 +00:00
Evan Cheng
c5fb2b14ca Add 128-bit pmovmskb intrinsic support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27255 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 00:33:26 +00:00
Evan Cheng
591f740a40 Change SSE pack operation definitions to fit what the intrinsics expected. 
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27254 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 23:53:14 +00:00
Evan Cheng
4e27b8e8f4 Add SSE2 integer pack with saturation intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27253 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 23:09:19 +00:00
Evan Cheng
506d3dfa90 - Added some SSE2 128-bit packed integer ops. 
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27252 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 23:07:14 +00:00
Evan Cheng
75658b96bf Add a pshufhw test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27251 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 22:51:28 +00:00
Evan Cheng
691c923e47 Need to special case splat after all. Make the second operand of splat 
vector_shuffle undef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27250 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 19:02:40 +00:00
Evan Cheng
e4086e5086 Use unpcklpd for v2f64 splat. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27249 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 18:59:48 +00:00
Evan Cheng
5aa97b200b Floating point logical operation patterns should match bit_convert. Or else 
integer vector logical operations would match andp{s|d} instead of pand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27248 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 18:47:40 +00:00
Evan Cheng
074fd57fbd Add more SSE intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 06:07:16 +00:00
Evan Cheng
475aecf467 - More shuffle related bug fixes. 
- Whenever possible use ops of the right packed types for vector shuffles /
  splats.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27246 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 03:04:49 +00:00
Evan Cheng
c999c745c0 Another entry about shuffles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27245 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 03:03:46 +00:00
Evan Cheng
4f5633883b - Only use pshufd for v4i32 vector shuffles. 
- Other shuffle related fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27244 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 01:30:51 +00:00
Chris Lattner
f3a627262c add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27243 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 00:24:13 +00:00
Chris Lattner
246ce96db9 new testcase 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27242 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 00:12:08 +00:00
Chris Lattner
2bbd81064a Bug fixes: handle constantexpr insert/extract element operations 
Handle constantpacked vectors with constantexpr elements.

This fixes CodeGen/Generic/vector-constantexpr.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27241 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 00:11:43 +00:00
Evan Cheng
c46349de29 Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics. 
The source operands type are v4sf with upper bits passes through.
Added matching code for these.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27240 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 23:51:43 +00:00
Evan Cheng
36b27f3cde Fixing buggy code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27239 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 23:41:33 +00:00
Evan Cheng
f065a6f711 Don't sort the names before outputing the intrinsic name table. It causes a 
mismatch against the enum table.
This is a part of Sabre's master plan to drive me nuts with subtle bugs that
happens to only affect x86 be. :-)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27237 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 22:25:56 +00:00
Chris Lattner
cef896e50c When building a VVECTOR_SHUFFLE node from extract_element operations, make 
sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).

The later is not canonical form, and prevents the PPC splat pattern from
matching.  For a particular splat, we go from generating this:

	li r10, lo16(LCPI1_0)
	lis r11, ha16(LCPI1_0)
	lvx v3, r11, r10
	vperm v3, v2, v2, v3

to generating:

	vspltw v3, v2, 3


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27236 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 22:19:47 +00:00
Chris Lattner
66445d3e0a Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y') 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27235 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 22:11:53 +00:00
Chris Lattner
bfc1a79c5b new testcase 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27234 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 20:32:12 +00:00
Chris Lattner
d7648c8934 Turn a series of extract_element's feeding a build_vector into a 
vector_shuffle node.  For this:

void test(__m128 *res, __m128 *A, __m128 *B) {
  *res = _mm_unpacklo_ps(*A, *B);
}

we now produce this code:

_test:
        movl 8(%esp), %eax
        movaps (%eax), %xmm0
        movl 12(%esp), %eax
        unpcklps (%eax), %xmm0
        movl 4(%esp), %eax
        movaps %xmm0, (%eax)
        ret

instead of this:

_test:
        subl $76, %esp
        movl 88(%esp), %eax
        movaps (%eax), %xmm0
        movaps %xmm0, (%esp)
        movaps %xmm0, 32(%esp)
        movss 4(%esp), %xmm0
        movss 32(%esp), %xmm1
        unpcklps %xmm0, %xmm1
        movl 84(%esp), %eax
        movaps (%eax), %xmm0
        movaps %xmm0, 16(%esp)
        movaps %xmm0, 48(%esp)
        movss 20(%esp), %xmm0
        movss 48(%esp), %xmm2
        unpcklps %xmm0, %xmm2
        unpcklps %xmm1, %xmm2
        movl 80(%esp), %eax
        movaps %xmm2, (%eax)
        addl $76, %esp
        ret

GCC produces this (with -fomit-frame-pointer):

_test:
        subl    $12, %esp
        movl    20(%esp), %eax
        movaps  (%eax), %xmm0
        movl    24(%esp), %eax
        unpcklps        (%eax), %xmm0
        movl    16(%esp), %eax
        movaps  %xmm0, (%eax)
        addl    $12, %esp
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27233 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 20:28:38 +00:00
Chris Lattner
5b2316e2b0 Teach Legalize how to pack VVECTOR_SHUFFLE nodes into VECTOR_SHUFFLE nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27232 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 20:24:43 +00:00
Chris Lattner
354cde9a7e new node 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27231 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 19:54:42 +00:00
Chris Lattner
eda6dfd5e4 Add a new node 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27230 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 19:54:11 +00:00
Chris Lattner
4fbdd59f4f Don't crash on X^X if X is a vector. Instead, produce a vector of zeros. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27229 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 19:11:05 +00:00
Chris Lattner
f35b29765b Add an assertion 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27228 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 19:04:49 +00:00
Chris Lattner
d732a2915b add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27227 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 18:56:23 +00:00
Jim Laskey
b3e7be25be Refactor address attributes. Add base register to frame info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27226 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 14:58:32 +00:00
Jim Laskey
a99791886d Expose base register for DwarfWriter. Refactor code accordingly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27225 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 13:48:33 +00:00
Jim Laskey
bf7637d590 More bulletproofing of llvm.dbg.declare. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27224 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 13:45:20 +00:00
Jim Laskey
2d2a6131da Added missing paren on behalf of Ramana Radhakrishnan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27223 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 10:17:11 +00:00
Evan Cheng
ed4ca7f6c3 Missed X86::isUNPCKHMask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27222 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 08:27:15 +00:00
Evan Cheng
9bbfd4f68c movlps and movlpd should be modeled as two address code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27221 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 07:01:28 +00:00
Evan Cheng
6a6d354d4c Update 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27220 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 06:55:45 +00:00
Evan Cheng
be296ac5ca Typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27219 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 06:53:49 +00:00
Evan Cheng
2064a2b47e * Prefer using operation of matching types. e.g unpcklpd rather than movlhps. 
* Bug fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27218 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 06:50:32 +00:00
Evan Cheng
ec1ab444a1 Use movhpd is even better than movlhps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27217 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 06:40:57 +00:00
Nate Begeman
816cee2216 Fix a couple typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27216 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 04:18:18 +00:00
Nate Begeman
98e70cc124 Add a few more altivec intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27215 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 04:15:58 +00:00
Jeff Cohen
5659b41311 Keep Visual Studio informed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27214 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 04:01:27 +00:00
Chris Lattner
9bade4de9d These don't directly map to gcc intrinsics any more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27213 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 03:52:36 +00:00
Evan Cheng
4c4a2e2a0d Added a couple of entries about movhps and movlhps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27212 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 02:49:12 +00:00
Evan Cheng
000e4dd54b All unpack cases are now being handled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27211 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 02:44:05 +00:00
Evan Cheng
4fcb922c70 - Clean up / consoladate various shuffle masks. 
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27210 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 02:43:26 +00:00
Chris Lattner
ecc219b8d4 implement a bunch more intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27209 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 02:29:37 +00:00
Chris Lattner
858b35eaf7 Add some more intrinsics: rotates, fp rounds, and random other fp instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27208 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 02:28:48 +00:00
Evan Cheng
78b9ec3820 getVectorTyppe(MVT::i64, 2) ==> MVT::v2i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27207 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 01:59:17 +00:00