Commit Graph

103186 Commits

Author SHA1 Message Date
Tom Stellard
1d8e31fc7a R600/SI: Teach moveToVALU how to handle some SMRD instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:31:29 +00:00
Chad Rosier
fa2e88da1c [ARM64][fast-isel] Fast-isel doesn't know how to handle f128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207659 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:29:57 +00:00
Rafael Espindola
3dbcd2e69e Rename the test, it is testing the symver directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207658 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:27:44 +00:00
Matheus Almeida
6c71a5f6e4 [mips] Add instruction alias (sll and srl).
Summary:
The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which
is just a shorthand version of sllv/srlv $rd, $rt, $rs.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3483

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207657 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:23:04 +00:00
Sasa Stankovic
fbe7448e5d [mips] Fix MipsLongBranch pass to work when the offset from the branch to the
target cannot be determined accurately. This is the case for NaCl where the
sandboxing instructions are added in MC layer, after the MipsLongBranch pass.
It is also the case when the code has inline assembly. Instead of calculating
offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2)
expressions that are resolved during the fixup.

This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll
and implements microMIPS CHECKs in a much simpler way in a file
test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207656 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:06:25 +00:00
Matheus Almeida
99b44bacab [mips] Update tests with encoding information for slt, slti, sltiu and sltu.
Summary:
Also renamed non-portable register names (e.g. $t2) so that we don't end up
with a different encoding for what appears to be an equivalent instruction.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3505

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207655 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 14:52:57 +00:00
Tom Stellard
d3f1202966 R600: Remove unused function AMDGPUSubtarget::getDefaultSize()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207654 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 14:20:53 +00:00
Evgeniy Stepanov
55f8c07504 [asan] Disable asm instrumentation on unsupported platforms.
Only emit calls to compiler-rt asm routines on platforms where they are
present (currently limited to linux i386/x86_64).

Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207651 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 14:04:31 +00:00
Tim Northover
ee053f4f51 ARM64: enable AArch64's basic-a64-instructions test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207650 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:37:10 +00:00
Tim Northover
44a2f5610d ARM64: print lsr instead of lsrv for variable shifts (etc)
The canonical syntax for shifts by a variable amount does not end with 'v', but
that syntax should be supported as an alias (presumably for legacy reasons).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207649 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:37:07 +00:00
Tim Northover
7870967ba1 ARM64: use 32-bit operations for uxtb & uxth
Testing will be enabled shortly with basic-a64-instructions.s

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207648 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:37:02 +00:00
Tim Northover
1636a5f44a AArch64/ARM64: allow smaller granule relocations on MOVZ/MOVN
Testing will be enabled shortly with basic-a64-instructions.s

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207647 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:36:59 +00:00
Tim Northover
bfb7bc89df AArch64/ARM64: copy support for bCC instead of b.CC across.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207646 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:36:56 +00:00
Tim Northover
36c7472106 AArch64/ARM64: expunge CPSR from the sources
AArch64 does not have a CPSR register in the same way that AArch32 does. Most
of its compiler-relevant roles have been taken over by the more specific NZCV
register (representing just the flags set by normal instructions).

Its system control functions still remain, but are now under the
pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR
instructions described in the reference manual.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207645 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:14:14 +00:00
Tim Northover
d805bf8d61 AArch64/ARM64: use HS instead of CS & LO instead of CC.
On instructions using the NZCV register, a couple of conditions have dual
representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and
unsigned-lower/carry-clear). The first of these is more descriptive in most
circumstances, so we should print it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207644 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:14:03 +00:00
Rafael Espindola
ff56f416a5 Grammar fix.
Thanks to Saleem Abdulrasool for noticing it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207643 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 12:42:22 +00:00
Daniel Sanders
1c8add9978 [mips][msa] Fix vector insertions where the index is variable
Summary:
This isn't supported directly so we rotate the vector by the desired number of
elements, insert to element zero, then rotate back.

The i64 case generates rather poor code on MIPS32. There is an obvious
optimisation to be made in future (do both insert.w's inside a shared 
rotate/unrotate sequence) but for now it's sufficient to select valid code
instead of aborting.

Depends on D3536

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3537

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207640 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 12:09:32 +00:00
Tim Northover
4e29e3a10a ARM64: accept ELF-relocated load/store insts without a #.
E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax
too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207639 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 12:00:20 +00:00
Tim Northover
cb87e23ce2 ARM64: remove duplication by templating InstPrinter methods
No functional change, so no tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207638 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:43:36 +00:00
Matheus Almeida
00bdeb4c54 [mips] Add support for .cpload.
Summary:
This directive is used for setting up $gp in the beginning of a function.
It expands to three instructions if PIC is enabled:
lui   $gp, %hi(_gp_disp)
addui $gp, $gp, %lo(_gp_disp)
addu  $gp, $gp, $reg

_gp_disp is a special symbol that the linker sets to the distance between
the lui instruction and the context pointer (_gp).

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3480

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207637 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:28:42 +00:00
Matheus Almeida
737de9db8e [mips] Emit all three relocation operations for each relocation entry on Mips64 big-endian systems.
Summary:
The N64 ABI allows up to three operations to be specified per relocation record
independently of the endianness.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3529

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:21:10 +00:00
Tim Northover
ebde5a5e49 ARM64: use hex immediates for movz/movk instructions
Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to
piece together an immediate in 16-bit chunks, hex is probably the most
appropriate format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207635 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:40 +00:00
Tim Northover
87476b607c ARM64: hexify printing various immediate operands
This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they
accept weird shifts which are more naturally understandable in hex notation).

Also changes BRK/HINT etc, which is probably a neutral change, but easier than
the alternative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
Tim Northover
2a2cce79be ARM64: print canonical syntax for add/sub (imm) instructions.
Since these instructions only accept a 12-bit immediate, possibly shifted left
by 12, the canonical syntax used by the architecture reference manual is "#N {,
lsl #12 }". We should accept an immediate that has already been shifted, (e.g.

Also, print a comment giving the full addend since it can be helpful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207633 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:15 +00:00
Chandler Carruth
491f476b8b [LCG] Add the really, *really* boring edge insertion case: adding an
edge entirely within an existing SCC. Shockingly, making the connected
component more connected is ... a total snooze fest. =]

Anyways, its wired up, and I even added a test case to make sure it
pretty much sorta works. =D

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207631 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 10:48:36 +00:00
Evgeniy Stepanov
0a78097774 Fix multiline comment warning.
../unittests/Analysis/LazyCallGraphTest.cpp:45:1: warning: multi-line comment [-Wcomment]
 //        /  \
 ^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207629 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 10:29:06 +00:00
James Molloy
d5acbbf90b [ARM64] Simplify if condition.
v2f32 and v4f32 were missed out of these conditions, so this is also
a bugfix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207628 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 10:15:50 +00:00
James Molloy
d98970d80d [ARM64] Fix stupid copy-pasto in ARM64MCAsmInfo.cpp - aarch64_be -> arm64_be
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207627 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 10:15:46 +00:00
James Molloy
44ff92f64a [ARM64] Try and make the ELF MCJIT *slightly* less broken for ARM64.
A bunch of switch cases were missing, not just for ARM64 but also for
AArch64_BE. I've fixed all those, but there's zero testing as
ExecutionEngine tests are disabled when crosscompiling and I don't
have a native platform available to test on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207626 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 10:15:41 +00:00
James Molloy
c447befac4 [ARM64] Ensure arm64_be is dealt with when emitting debug info.
This is a partial port of r204816 (cpirker "Elf support for MC-JIT
runtime dynamic linker") from AArch64 to ARM64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207625 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 10:15:35 +00:00
NAKAMURA Takumi
5f4aba6c8a raw_ostream::operator<<(StringRef): Avoid potential overflow in pointer arithmetic.
(OutBufCur + Size) might overflow if Size were large. For example on i686-linux,

  OutBufCur: 0xFFFDF27D
  OutBufEnd: 0xFFFDF370
  Size:      0x0002BF20 (180,000)

It caused flaky error in MC/COFF/section-name-encoding.s.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 09:33:50 +00:00
Tim Northover
5b188b1cb8 ARM64: make sure FastISel uses a GPR64 source in 64-bit extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207620 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 09:32:01 +00:00
Chandler Carruth
6253c04fc9 [LCG] Actually test the *basic* edge removal bits (IE, the non-SCC
bits), and discover that it's totally broken. Yay tests. Boo bug. Fix
the basic edge removal so that it works by nulling out the removed edges
rather than actually removing them. This leaves the indices valid in the
map from callee to index, and preserves some of the locality for
iterating over edges. The iterator is made bidirectional to reflect that
it now has to skip over null entries, and the skipping logic is layered
onto it.

As future work, I would like to track essentially the "load factor" of
the edge list, and when it falls below a threshold do a compaction.

An alternative I considered (and continue to consider) is storing the
callees in a doubly linked list where each element of the list is in
a set (which is essentially the classical linked-hash-table
datastructure). The problem with that approach is that either you need
to heap allocate the linked list nodes and use pointers to them, or use
a bucket hash table (with even *more* linked list pointer overhead!),
etc. It's pretty easy to get 5x overhead for values that are just
pointers. So far, I think punching holes in the vector, and periodic
compaction is likely to be much more efficient overall in the space/time
tradeoff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207619 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 07:45:27 +00:00
Benjamin Kramer
28ea58283b Add a <tuple> include to more files that aren't getting it transitively on MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207617 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 07:21:01 +00:00
Craig Topper
7ae9b5fc71 Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I introduced most of these recently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207616 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 07:17:30 +00:00
Saleem Abdulrasool
ddbde80aae ARM: support stack probe emission for Windows on ARM
This introduces the stack lowering emission of the stack probe function for
Windows on ARM. The stack on Windows on ARM is a dynamically paged stack where
any page allocation which crosses a page boundary of the following guard page
will cause a page fault. This page fault must be handled by the kernel to
ensure that the page is faulted in. If this does not occur and a write access
any memory beyond that, the page fault will go unserviced, resulting in an
abnormal program termination.

The watermark for the stack probe appears to be at 4080 bytes (for
accommodating the stack guard canaries and stack alignment) when SSP is
enabled.  Otherwise, the stack probe is emitted on the page size boundary of
4096 bytes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207615 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 07:05:07 +00:00
NAKAMURA Takumi
38dbc84602 ConstantHoisting.cpp: Add <tuple> for std::tie, since r207593 removed FileSystem.h, it includes <tuple>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207614 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 06:44:50 +00:00
Saleem Abdulrasool
f3ce0c061e ARM: print COFF function header for Windows on ARM
Emit the COFF header when printing out the function.  This is important as the
header contains two important pieces of information: the storage class for the
symbol and the symbol type information.  This bit of information is required for
the linker to correctly identify the type of symbol that it is dealing with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207613 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 06:14:25 +00:00
Craig Topper
25d437f45d [C++11] Use 'nullptr' in tablegen output files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207611 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 05:53:35 +00:00
Craig Topper
c6b0620101 De-virtualize or remove some methods that have no overrides nor override anything. In some cases remove all together if there are no callers either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207610 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 05:53:27 +00:00
Saleem Abdulrasool
38bd5c4bf9 ARM: move llvm_unreachable use
When building with -Werror=covered-switch-default (as on the buildbots), the
build would fail since all cases are covered by the switch.  Move the
llvm_unreachable to the end of the function as an annotation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207609 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 05:12:41 +00:00
Saleem Abdulrasool
745fff806d ARM: partially handle 32-bit relocations for WoA
IMAGE_REL_ARM_MOV32T relocations require that the movw/movt pair-wise
relocation is not split up and reordered. When expanding the mov32imm
pseudo-instruction, create a bundle if the machine operand is referencing an
address.  This helps ensure that the relocatable address load is not reordered
by subsequent passes.

Unfortunately, this only partially handles the case as the Constant Island Pass
occurs after the instructions are unbundled and does not properly handle
bundles.  That is a more fundamental issue with the pass itself and beyond the
scope of this change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207608 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 04:54:58 +00:00
Rafael Espindola
c8556d725f Simplify getSymbolOffset.
We can now use EvaluateAsValue to make it non recursive and remove some code
duplication.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 03:06:06 +00:00
Chandler Carruth
91cc1431cb [ADT] Provide some helpful static_asserts for using operations of the
wrong iterator category. These aren't comprehensive, but they have
caught the common cases for me and produce much nicer errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207601 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 00:49:32 +00:00
Alexey Samsonov
1ea858937c [DWARF parser] Cleanup code in DWARFDebugLine.
Streamline parsing and dumping line tables:
Prefer composition to multiple inheritance in DWARFDebugLine::ParsingState.
Get rid of the weird concept of "DumpingState" structure.

was:
  DWARFDebugLine::DumpingState state(OS);
  DWARFDebugLine::parseStatementTable(..., state);
now:
  DWARFDebugLine::LineTable LineTable;
  LineTable.parse(...);
  LineTable.dump(OS);

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207599 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 00:09:19 +00:00
Reid Kleckner
9902128e2a Implement X86 code generation for musttail
Currently, musttail codegen is relying on sibcall optimization, and
reporting a fatal error if fails.  Sibcall optimization fails when stack
arguments need to be modified, which is insufficient for musttail.

The logic for moving arguments in memory safely is already implemented
for GuaranteedTailCallOpt.  This change merely arranges for musttail
calls to use it.

No functional change for GuaranteedTailCallOpt.

Reviewers: espindola

Differential Revision: http://reviews.llvm.org/D3493

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207598 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:55:41 +00:00
Reid Kleckner
fc288c8339 Fix the build with MSVC 2013 by explicitly requesting llvm::make_unique
MSVC 2013 provides std::make_unique, which it finds with ADL when one of
the parameters is std::unique_ptr, leading to an ambiguous overload.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207597 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:54:52 +00:00
Benjamin Kramer
d17f593e72 Another missing include for MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207596 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:46:48 +00:00
David Blaikie
62db473b50 Fix some 80 cols violations committed in r207539
Caught by Eric Christopher in post-commit review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207595 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:43:06 +00:00
Benjamin Kramer
ba8848470e Try to fix the msvc build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207594 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:37:02 +00:00