Commit Graph

1145 Commits

Author SHA1 Message Date
Bob Wilson
a96751fc8f Provide InitializeAllTargets and InitializeNativeTarget functions in the
C bindings.  Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74026 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 23:59:40 +00:00
Douglas Gregor
bcba7f95c2 Work around build problem with OpenJDK, which defines X86 as a
macro. Fixes PR 4427. Patch by Xerxes Rånby!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 17:21:35 +00:00
Bruno Cardoso Lopes
0d3193ef3c Add more methods to gather target specific elf stuff
Support for .text relocations, implementing TargetELFWriter overloaded methods for x86/x86_64.
Use a map to track global values to their symbol table indexes
Code cleanup and small fixes



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22 19:16:16 +00:00
Chris Lattner
c12430644a implement support for lowering subregs when preparing to print
LEA64_32r, eliminating a bunch of modifier logic stuff on addr modes.

Implement support for printing mbb labels as operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73817 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 07:03:18 +00:00
Devang Patel
1e86a66b00 mv CodeGen/DebugLoc.h Support/DebugLoc.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73786 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 22:08:58 +00:00
Chris Lattner
4e0f25b603 merge the common darwin settings from the X86/PPC/ARM targets
into DarwinTargetAsmInfo.cpp.  The remaining differences should
be evaluated.  It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 00:08:39 +00:00
Chris Lattner
a93ca92379 move mangler quote handling from asm printers to TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73738 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:41:35 +00:00
Chris Lattner
b839c3f577 simplify macro debug info directive handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73736 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:31:37 +00:00
Evan Cheng
f9f1da17f8 - Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 02:04:01 +00:00
Chris Lattner
5f1a5c7f57 Add a utility header that makes it easy to link in the right set
of targets for various purposes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 16:42:01 +00:00
Anton Korobeynikov
0d492bdf4d Address more comments :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73430 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 22:08:48 +00:00
Anton Korobeynikov
52edfc7a6d Document ABIType enum. Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73427 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 21:46:02 +00:00
Evan Cheng
358dec5180 Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 08:28:29 +00:00
Evan Cheng
90f95f88c6 Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14 20:22:55 +00:00
Bruno Cardoso Lopes
ae9163f0e2 Introduce new BinaryObject (blob) class, ELF Writer modified to use it. BinaryObject.h by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73333 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14 07:53:21 +00:00
Bruno Cardoso Lopes
d00d4159d4 Use forward declarations and move TargetELFWriterInfo impl to a new file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73209 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-11 22:13:00 +00:00
Bruno Cardoso Lopes
c997d45ae5 Support for ELF Visibility
Emission for globals, using the correct data sections
Function alignment can be computed for each target using TargetELFWriterInfo
Some small fixes



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73201 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-11 19:16:03 +00:00
David Greene
f5aefbdb79 Change IndexedModeAction representation.
This changes the IndexedModeAction representation to remove the
limitation on the number of value types in MVT.  This limitation
prevents us from specifying AVX types.

Prior to this change IndexedModActions was represented as follows...

uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];

the first dimension was used to represent loads, then stores.  This
imposed a limitation of 32 on the number of value types that could be
handled with this method.  The value type was used to shift the two bits
into and out of the approprate bits in the uint64_t.

With this change the array is now represented as ...

uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];

Takes more space but removes the limitation on MVT::LAST_VALUETYPE.  The
first dimension is now the value_type for the reference.  The second
dimension is the load [0] vs. store[1].  The third dimension represents
the various modes for load store.  Accesses are now direct, no shifting
or masking.

There are other limitations that need to be removed, so that
MVT::LAST_VALUETYPE can be greater than 32.  This is merely the first
step towards that goal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73104 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-09 00:19:10 +00:00
David Greene
63ec51d86b Oops, didn't mean to commit 73102 yet. Revert it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73103 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 23:54:42 +00:00
David Greene
9df4eb8cfe Change IndexedModeAction representation.
This changes the IndexedModeAction representation to remove the
limitation on the number of value types in MVT.  This limitation
prevents us from specifying AVX types.

Prior to this change IndexedModActions was represented as follows...

uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];

the first dimension was used to represent loads, then stores.  This
imposed a limitation of 32 on the number of value types that could be
handled with this method.  The value type was used to shift the two bits
into and out of the approprate bits in the uint64_t.

With this change the array is now represented as ...

uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];

Takes more space but removes the limitation on MVT::LAST_VALUETYPE.  The
first dimension is now the value_type for the reference.  The second
dimension is the load [0] vs. store[1].  The third dimension represents
the various modes for load store.  Accesses are now direct, no shifting
or masking.

There are other limitations that need to be removed, so that
MVT::LAST_VALUETYPE can be greater than 32.  This is merely the first
step towards that goal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73102 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 23:53:19 +00:00
Anton Korobeynikov
0eebf653a7 The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 22:53:56 +00:00
David Greene
e1b469170b Make IntInits and ListInits typed. This helps deduce types of !if and
other operators.  For the rare cases where a list type cannot be
deduced, provide a []<type> syntax, where <type> is the list element
type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73078 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 20:23:18 +00:00
Bruno Cardoso Lopes
f5b0c5a1c7 Remove elf specific info from ELFWriter.h to Elf.h. Code cleanup and more comments added
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72982 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 03:56:29 +00:00
Devang Patel
578efa920a Add new function attribute - noimplicitfloat
Update code generator to use this attribute and remove NoImplicitFloat target option.
Update llc to set this attribute when -no-implicit-float command line option is used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72959 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 21:57:13 +00:00
Nate Begeman
abc0199680 Adapt the x86 build_vector dagcombine to the current state of the legalizer.
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector 
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.

Teach the build_vector dag combine in x86 back end to recognize consecutive 
loads producing the low part of the vector.

Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.

Add a testcase for the transform.

Old:
	subl	$28, %esp
	movl	32(%esp), %eax
	movl	4(%eax), %ecx
	movl	%ecx, 4(%esp)
	movl	(%eax), %eax
	movl	%eax, (%esp)
	movaps	(%esp), %xmm0
	pmovzxwd	%xmm0, %xmm0
	movl	36(%esp), %eax
	movaps	%xmm0, (%eax)
	addl	$28, %esp
	ret

New:
	movl	4(%esp), %eax
	pmovzxwd	(%eax), %xmm0
	movl	8(%esp), %eax
	movaps	%xmm0, (%eax)
	ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72957 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 21:37:30 +00:00
Devang Patel
d18e31ae17 Add new function attribute - noredzone.
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:05:33 +00:00
Dale Johannesen
874ae251c3 Revert 72707 and 72709, for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02 03:12:52 +00:00
Dale Johannesen
4150d83abe Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 23:27:20 +00:00
Bruno Cardoso Lopes
a3f99f9033 First patch in the direction of splitting MachineCodeEmitter in two subclasses:
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30 20:51:52 +00:00
Bill Wendling
4d4eab219a Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72603 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30 00:58:37 +00:00
Evan Cheng
abdbc57abb Default isNarrowingProfitable to false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72561 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-29 05:31:40 +00:00
Evan Cheng
8b944d39b3 Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
e.g.
orl     $65536, 8(%rax)
=>
orb     $1, 10(%rax)

Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 00:35:15 +00:00
Anton Korobeynikov
41a024385f Propagate CPU string out of SubtargetFeatures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 19:50:50 +00:00
Evan Cheng
6ebf7bc740 Run code placement optimization for targets that want it (arm and x86 for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71726 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 21:42:09 +00:00
Dan Gohman
f46ef0450f Clarify a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71561 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-12 17:08:34 +00:00
Jay Foad
8d730fbde5 Don't #include DerivedTypes.h from TargetData.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11 19:38:09 +00:00
Dan Gohman
20b7ca1eb9 Add a comment about the special meaning of VoidTy in this context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71466 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11 19:11:53 +00:00
Jay Foad
7524b59062 Change TargetData::getIntPtrType() to return an IntegerType instead of
just a Type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71426 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11 11:13:47 +00:00
Duncan Sands
777d2306b3 Rename PaddedSize to AllocSize, in the hope that this
will make it more obvious what it represents, and stop
it being confused with the StoreSize.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71349 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-09 07:06:46 +00:00
Duncan Sands
2a6e0a2140 Add some examples to show the difference between
the various notions of type size used in LLVM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71230 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-08 17:49:48 +00:00
Evan Cheng
d923fc621f Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70950 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-05 00:30:09 +00:00
Evan Cheng
c781a243a3 In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.

Not yet enabled. This is part 1. More coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70787 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-03 18:32:42 +00:00
Jakob Stoklund Olesen
ba67d87fe4 getCommonSubClass() - Calculate the largest common sub-class of two register
classes.

This is implemented as a function rather than a method on TargetRegisterClass
because it is symmetric in its arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70512 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30 21:23:32 +00:00
Bill Wendling
581b93415e Remove unused flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70459 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30 00:57:51 +00:00
Bill Wendling
b8cb0bb08c Remove LTO optimization level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70445 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 23:40:42 +00:00
Bill Wendling
98a366d547 Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 23:29:43 +00:00
Sanjiv Gupta
b27fa0afe2 Add directive to declare external globals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 08:23:18 +00:00
Nate Begeman
5a5ca1519e Implement review feedback for vector shuffle work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 05:20:52 +00:00
Bill Wendling
be8cc2a3de Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 00:15:41 +00:00
Bill Wendling
a24d1b1558 Correct comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70340 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 00:09:22 +00:00