Commit Graph

25774 Commits

Author SHA1 Message Date
Reed Kotler
1e07de3529 Add another intrinsic that LLVM gives an incorrect prototype to.
I need to go through all the runtime routine list and see if there
are any more I need to add for mips16 floating point. Prototypes must
be correct or else I don't know to add a helper function call.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188106 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09 21:33:41 +00:00
Benjamin Kramer
fc6434a73d Add a overload to CostTable which allows it to infer the size of the table.
Use it to avoid repeating ourselves too often. Also store MVT::SimpleValueType
in the TTI tables so they can be statically initialized, MVT's constructors
create bloated initialization code otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188095 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09 19:33:32 +00:00
Mihai Popa
04b03fac11 This fixes the Thumb2 CPS assembly syntax.
In Thumb1, only one variant is supported: CPS{effect} {flags}

Thumb2 supports three:
CPS{effect}.W {flags}
CPS{effect} {flags} {mode}
CPS {mode}

Canonically, .W should be used only when ambiguity is present between encodings of different width.
The wide suffix is still accepted for the latter two forms via aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188071 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09 13:52:32 +00:00
Mihai Popa
e921f32353 Fix assembling of Thumb2 branch instructions.
The long encoding for Thumb2 unconditional branches is broken.
Additionally, there is no range checking for target operands; as such 
for instructions originating in assembly code, only short Thumb encodings
are generated, regardless of the bitsize needed for the offset.

Adding range checking is non trivial due to the representation of Thumb
branch instructions. There is no true difference between conditional and
unconditional branches in terms of operands and syntax - even unconditional
branches have a predicate which is expected to match that of the IT block
they are in. Yet, the encodings and the permitted size of the offset differ.

Due to this, for any mnemonic there are really 4 encodings to choose for.

The problem cannot be handled in the parser alone or by manipulating td files.
Because the parser builds first a set of match candidates and then checks them
one by one, whatever tablegen-only solution might be found will ultimately be
dependent of the parser's evaluation order. What's worse is that due to the fact
that all branches have the same syntax and the same kinds of operands, that 
order is governed by the lexicographical ordering of the names of operand 
classes...

To circumvent all this, any necessary disambiguation is added to the instruction
validation pass.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09 10:38:32 +00:00
Richard Sandiford
6514751d12 [SystemZ] Update README
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188062 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09 09:25:57 +00:00
Jack Carter
d12fce1a27 Mips ELF: MicroMips direct object Little endian support.
Test included.

Patch by Zoran Jovanovich


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188024 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 23:30:40 +00:00
Michael J. Spencer
081a1941b5 [Object] Split the ELF interface into 3 parts.
* ELFTypes.h contains template magic for defining types based on endianess, size, and alignment.
* ELFFile.h defines the ELFFile class which provides low level ELF specific access.
* ELFObjectFile.h contains ELFObjectFile which uses ELFFile to implement the ObjectFile interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188022 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 22:27:13 +00:00
Akira Hatanaka
491d04969d [mips] Rename accumulator register classes and FP register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:54:26 +00:00
Akira Hatanaka
7af40bfa66 [mips] Mark pseudo instructions as code-gen only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188017 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:44:39 +00:00
Akira Hatanaka
94a88c49b0 [mips] Delete register class HWRegs64.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188016 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:37:32 +00:00
David Fang
d76adee1b2 cast fix to appease buildbot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:29:30 +00:00
David Fang
d4f9d05fde initial draft of PPCMachObjectWriter.cpp
this records relocation entries in the mach-o object file
for PIC code generation.
tested on powerpc-darwin8, validated against darwin otool -rvV

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188004 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 20:14:40 +00:00
Niels Ole Salscheider
014773626d R600/SI: Implement fp32<->fp64 conversions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187988 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 16:06:15 +00:00
Niels Ole Salscheider
7114e2e7cf R600/SI: Implement sint<->fp64 conversions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 16:06:08 +00:00
Jakub Staszak
91955e78e7 Use pop_back() instead of pop_back_val() when the returned value is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 15:48:46 +00:00
Silviu Baranga
cee3538233 Remove the now redundant FeatureFP16 from the Cortex-A15 feature list. It was made redundant when FeatureVFP4 was added which implies FP16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 15:47:33 +00:00
Jakub Staszak
72feef14f1 Fix the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 15:19:25 +00:00
Mihai Popa
868bed9967 The name "tCDP" isn't used anywhere else in the source code, so renaming it for consistency doesn't cause any problems.
This is the only Thumb2 instruction defined with "t" prefix; all other Thumb2 instructions have "t2" prefix (e.g. "t2CDP2" which is defined immediately afterwards).

Patch by Artyom Skrobov.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 10:20:41 +00:00
Hal Finkel
05a4d2642b PPC: Map frin to round() not nearbyint() and rint()
Making use of the recently-added ISD::FROUND, which allows for custom lowering
of round(), the PPC backend will now map frin to round(). Previously, we had
been using frin to lower nearbyint() (and rint() via some custom lowering to
handle the extra fenv flags requirements), but only in fast-math mode because
frin does not tie-to-even. Several users had complained about this behavior,
and this new mapping of frin to round is certainly more appropriate (and does
not require fast-math mode).

In effect, this reverts r178362 (and part of r178337, replacing the nearbyint
mapping with the round mapping).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187960 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 04:31:34 +00:00
Hal Finkel
41418d17cc Add ISD::FROUND for libm round()
All libm floating-point rounding functions, except for round(), had their own
ISD nodes. Recent PowerPC cores have an instruction for round(), and so here I'm
adding ISD::FROUND so that round() can be custom lowered as well.

For the most part, this is straightforward. I've added an intrinsic
and a matching ISD node just like those for nearbyint() and friends. The
SelectionDAG pattern I've named frnd (because ISD::FP_ROUND has already claimed
fround).

This will be used by the PowerPC backend in a follow-up commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187926 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 22:49:12 +00:00
Elena Demikhovsky
207600d2cf AVX-512 set: Added BROADCAST instructions
with lowering logic and a test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 12:34:55 +00:00
Richard Sandiford
29e873ddb6 [SystemZ] Optimize floating-point comparisons with zero
This follows the same lines as the integer code.  In the end it seemed
easier to have a second 4-bit mask in TSFlags to specify the compare-like
CC values.  That eats one more TSFlags bit than adding a CCHasUnordered
would have done, but it feels more concise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187883 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 11:10:06 +00:00
Richard Sandiford
e0bbf7288c [SystemZ] Add floating-point load-and-test instructions
These instructions can also be used as comparisons with zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 11:03:34 +00:00
Craig Topper
b19982c42b Simplify code. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187870 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 08:16:07 +00:00
Evgeniy Stepanov
8f3562bc6b Initialize SIInsertWaits::ExpInstrTypesSeen in the pass constructor.
This value may be used uninitialized in SIInsertWaits::insertWait.
Found with MemorySanitizer.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187869 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 07:47:41 +00:00
Reed Kotler
51c9043f3b Create a pattern for the "trap" instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187863 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 04:00:26 +00:00
David Blaikie
040ef013ac Remove unused functions introduced in r172685 to unbreak the Clang -Werror build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187838 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 00:25:12 +00:00
Tom Stellard
c89c964499 R600: Add new file from r187831 to CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:12:34 +00:00
Akira Hatanaka
1858786285 [mips] Rename register classes CPURegs and CPU64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:08:38 +00:00
Tom Stellard
3492eefa4b R600/SI: Use VSrc_* register classes as the default classes for types
Since the VSrc_* register classes contain both VGPRs and SGPRs, copies
that used be emitted by isel like this:

SGPR = COPY VGPR

Will now be emitted like this:

VSrC = COPY VGPR

This patch also adds a pass that tries to identify and fix situations where
a VGPR to SGPR copy may occur.  Hopefully, these changes will make it
impossible for the compiler to generate illegal VGPR to SGPR copies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187831 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:08:28 +00:00
Tom Stellard
3406d882c0 R600/SI: Add more special cases for opcodes to ensureSRegLimit()
Also factor out the register class lookup to its own function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:08:18 +00:00
Justin Holewinski
06d63b31be [NVPTX] We dont have any target specific flags yet for generating symbol references, so get rid of the default-only switch statement. Fixes an MSVC warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:06:42 +00:00
Akira Hatanaka
6b034bb3ae [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of
instructions defined in MipsInstrInfo.td as codegen-only instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:01:10 +00:00
Akira Hatanaka
014096e4d5 [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 22:35:29 +00:00
Akira Hatanaka
a1fe9ef62e [mips] Replace usages of register classes with register operands. Also, remove
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 22:20:40 +00:00
Hal Finkel
0e910d2cb5 Add PPC64 mulli pattern
The PPC backend had been missing a pattern to generate mulli for 64-bit
multiples. We had been generating it only for 32-bit multiplies. Unfortunately,
generating li + mulld unnecessarily increases register pressure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 17:03:03 +00:00
Mihai Popa
4f7092176c This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 16:07:46 +00:00
Mihai Popa
4a378b95aa Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc instead of apsr_nzcv)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187803 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 15:52:36 +00:00
Justin Holewinski
df66ff09bc [NVPTX] Add missing patterns for i1 [s,u]int_to_fp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187800 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 14:13:34 +00:00
Justin Holewinski
a3635eefc7 [NVPTX] Fix bug in stack code generation causes by MC conversion
We do use a very small set of physical registers, so account for
them in the virtual register encoding between MachineInstr and MC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187799 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 14:13:31 +00:00
Justin Holewinski
82767327c5 [NVPTX] Start conversion to MC infrastructure
This change converts the NVPTX target to use the MC infrastructure
instead of directly emitting MachineInstr instances. This brings
the target more up-to-date with LLVM TOT, and should fix PR15175
and PR15958 (libNVPTXInstPrinter is empty) as a side-effect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 14:13:27 +00:00
Tim Northover
8775a51d94 ARM: implement allowTruncateForTailCall
Now that it's in place, it seems silly not to let ARM make use of the extra
tail call opportunities.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187795 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 13:58:03 +00:00
Tim Northover
d113448c1d Refactor isInTailCallPosition handling
This change came about primarily because of two issues in the existing code.
Niether of:

define i64 @test1(i64 %val) {
  %in = trunc i64 %val to i32
  tail call i32 @ret32(i32 returned %in)
  ret i64 %val
}

define i64 @test2(i64 %val) {
  tail call i32 @ret32(i32 returned undef)
  ret i32 42
}

should be tail calls, and the function sameNoopInput is responsible. The main
problem is that it is completely symmetric in the "tail call" and "ret" value,
but in reality different things are allowed on each side.

For these cases:
1. Any truncation should lead to a larger value being generated by "tail call"
   than needed by "ret".
2. Undef should only be allowed as a source for ret, not as a result of the
   call.

Along the way I noticed that a mismatch between what this function treats as a
valid truncation and what the backends see can lead to invalid calls as well
(see x86-32 test case).

This patch refactors the code so that instead of being based primarily on
values which it recurses into when necessary, it starts by inspecting the type
and considers each fundamental slot that the backend will see in turn. For
example, given a pathological function that returned {{}, {{}, i32, {}}, i32}
we would consider each "real" i32 in turn, and ask if it passes through
unchanged. This is much closer to what the backend sees as a result of
ComputeValueVTs.

Aside from the bug fixes, this eliminates the recursion that's going on and, I
believe, makes the bulk of the code significantly easier to understand. The
trade-off is the nasty iterators needed to find the real types inside a
returned value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187787 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 09:12:35 +00:00
Craig Topper
5923547e2a Simplify vector lane handling math a bit. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 07:23:12 +00:00
Craig Topper
57bc5a0b5b Simplify math a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187781 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 06:54:25 +00:00
NAKAMURA Takumi
8e1d64666f Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 06:38:37 +00:00
Craig Topper
aa0f420567 Replace EVT with MVT in isHorizontalBinOp as it is only called with legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187779 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 06:05:05 +00:00
Craig Topper
20b46b0733 Simplify code slightly. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187771 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 04:12:40 +00:00
Tom Stellard
01d7203ef8 Factor FlattenCFG out from SimplifyCFG
Patch by: Mei Ye

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187764 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 02:43:45 +00:00
Tom Stellard
2b272a1c8c R600: Implement TargetLowering::getVectorIdxTy()
We use MVT::i32 for the vector index type, because we use 32-bit
operations to caculate offsets when dynamically indexing vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187749 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 22:22:07 +00:00