Commit Graph

13321 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
1efd6b94a9 Use SmallPtrSet instead of DenseSet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 00:36:04 +00:00
Benjamin Kramer
d5f7690651 Give dagcombiner's worklist some inline capacity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 00:23:58 +00:00
Jakob Stoklund Olesen
9ab3dbe617 Assert on SSA errors in LiveVariables.
All uses of a virtual register must be dominated by its def.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152449 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 23:41:44 +00:00
Andrew Trick
fe4d6df5c7 misched: handle scheduler that insert instructions at empty region boundaries.
And add comments, since this is obviously confusing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152445 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 22:34:56 +00:00
Andrew Trick
1fabd9f85e misched: handle scheduling region boundaries nicely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152393 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 08:02:51 +00:00
Andrew Trick
68675c6c5b misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 04:29:02 +00:00
Andrew Trick
d24da97bbf misched comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152374 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 03:46:42 +00:00
Andrew Trick
7799eb40d4 revert 152356: verify misched changes using -misched=shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152373 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 03:46:39 +00:00
Andrew Trick
d04ec0c855 misched: allow the default scheduler to be one chosen by the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 00:52:20 +00:00
Evan Cheng
9ad62b3c09 Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152356 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 00:24:29 +00:00
Craig Topper
fac2598149 Use uint16_t to store instruction implicit uses and defs. Reduces static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08 08:22:45 +00:00
Stepan Dyatkovskiy
c10fa6c801 Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html

Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*".

ConstCaseIt is just a read-only iterator.
CaseIt is read-write iterator; it allows to change case successor and case value.

Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters.

Main way of iterator usage looks like this:
SwitchInst *SI = ... // intialize it somehow

for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) {
  BasicBlock *BB = i.getCaseSuccessor();
  ConstantInt *V = i.getCaseValue();
  // Do something.
}

If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method.
If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method.

There are also related changes in llvm-clients: klee and clang.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08 07:06:20 +00:00
Andrew Trick
c174eaf948 misched interface: Expose the MachineScheduler pass.
Allow targets to provide their own schedulers (subclass of
ScheduleDAGInstrs) to the misched pass. Select schedulers using
-misched=...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152278 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08 01:41:12 +00:00
Andrew Trick
7afcda0c58 Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152262 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 23:01:09 +00:00
Andrew Trick
ed395c8c47 misched prep: Expose the ScheduleDAGInstrs interface so targets may
implement their own MachineScheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152261 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 23:01:06 +00:00
Andrew Trick
ed8a0ecaa8 misched prep: Remove LLVM_LIBRARY_VISIBILITY from ScheduleDAGInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152260 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 23:01:02 +00:00
Andrew Trick
d790cada33 misched prep: Comment the ScheduleDAGInstrs interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 23:00:59 +00:00
Andrew Trick
035ec40eaf misched prep: Cleanup ScheduleDAGInstrs interface.
ScheduleDAGInstrs will be the main interface for MI-level
schedulers. Make sure it's readable: one page of protected fields, one
page of public methids.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 23:00:57 +00:00
Andrew Trick
21c535579b misched prep: remove extra "protected"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 23:00:54 +00:00
Andrew Trick
cf46b5acfd misched prep: rename InsertPos to End.
ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 23:00:52 +00:00
Andrew Trick
953be893e8 misched preparation: rename core scheduler methods for consistency.
We had half the API with one convention, half with another. Now was a
good time to clean it up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 23:00:49 +00:00
Chandler Carruth
b53a1d67b1 Try to clarify this comment some.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 10:13:40 +00:00
Chandler Carruth
fc22625eb0 Remove another outbreak of customized (and completely broken) hashing.
This one is particularly annoying because the hashing algorithm is
highly specialized, with a strange "equivalence" definition that subsets
the fields involved.

Still, this looks at the exact same set of data as the old code, but
without bitwise or-ing over parts of it and other mixing badness. No
functionality changed here. I've left a substantial fixme about the fact
that there is a cleaner and more principled way to do this, but it
requires making the equality definition actual stable for particular
types...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 09:39:46 +00:00
Bill Wendling
5b2749abf5 Where the BranchFolding pass removes a branch then adds another better branch,
the DebugLoc information can be maintained throughout by grabbing the DebugLoc
before the RemoveBranch and then passing the result to the InsertBranch.
Patch by Andrew Stanford-Jason!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152212 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 08:49:42 +00:00
Andrew Trick
8c1161a262 Fix cmake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152210 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:46:04 +00:00
Andrew Trick
6fd7dd6ba5 comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152209 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:54 +00:00
Andrew Trick
47c144505b misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.

ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.

ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.

Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.

- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.

- Added ScheduleDAGInstrs::begin()/end() public API.

- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:52 +00:00
Andrew Trick
7b58ae77ac ScheduleDAGInstrs comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:47 +00:00
Andrew Trick
84b454d1a2 misched preparation: modularize schedule emission.
ScheduleDAG has nothing to do with how the instructions are scheduled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:44 +00:00
Andrew Trick
73ba69b684 misched preparation: modularize schedule printing.
ScheduleDAG will not refer to the scheduled instruction sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:40 +00:00
Andrew Trick
4c72720427 misched preparation: modularize schedule verification.
ScheduleDAG will not refer to the scheduled instruction sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:36 +00:00
Andrew Trick
dbdca36af8 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:32 +00:00
Andrew Trick
0df7f8821c Added -view-misched=dags options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:25 +00:00
Andrew Trick
56b94c52c9 Cleanup in preparation for misched: Move DAG visualization logic.
Soon, ScheduleDAG will not refer to the BB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:22 +00:00
Andrew Trick
8ceaa660bf Added MachineBasicBlock::getFullName() to standardize/factor codegen diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152176 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:18 +00:00
Andrew Trick
acddd4963d whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152175 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:15 +00:00
Andrew Trick
084e179f09 Cleanup: DAG building is specific to either SD or MI scheduling. Not part of the target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:12 +00:00
Andrew Trick
e75537a243 misched comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:08 +00:00
Andrew Trick
6cfb14f6df misched: Use the StartBlock/FinishBlock hooks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:05 +00:00
Eric Christopher
8938895a83 Add the DW_AT_APPLE_runtime_class attribute to forward declarations
as well as completely defined classes.

This fixes rdar://10956070

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152171 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:15:19 +00:00
Evan Cheng
03be3622aa Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 23:33:32 +00:00
Jakob Stoklund Olesen
c511c2827d Hoist common code out of if statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 22:27:13 +00:00
Evan Cheng
8250d7385a Avoid finalizeBundles infinite looping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 02:00:52 +00:00
Owen Anderson
afd3d56b9d Make it possible for a target to mark FSUB as Expand. This requires providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 00:29:31 +00:00
Jim Grosbach
c6449b636f Make MCRegisterInfo available to the the MCInstPrinter.
Used to allow context sensitive printing of super-register or sub-register
references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 19:33:20 +00:00
Bill Wendling
c27faccb3c Fix warnings about adding a bool to a string.
Patch by Sean Silva!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152042 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 19:29:36 +00:00
Craig Topper
9ebfbf8b9f Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 05:37:41 +00:00
Jakob Stoklund Olesen
92b7df07af Stop fixing bad machine code in LiveIntervalAnalysis.
The first def of a virtual register cannot also read the register.
Assert on such bad machine code instead of trying to fix it.
TwoAddressInstructionPass should never create code like that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152010 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 19:19:10 +00:00
Jakob Stoklund Olesen
8d9c3a4ee7 Stop adding <imp-def> operands when coalescing sub-registers.
We are already setting <undef> flags, and that is good enough. The
<imp-def> operands don't mean anything any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152009 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 19:19:07 +00:00
Craig Topper
e4fd907e72 Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 10:43:23 +00:00