Commit Graph

7184 Commits

Author SHA1 Message Date
Devang Patel
1e86a66b00 mv CodeGen/DebugLoc.h Support/DebugLoc.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73786 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 22:08:58 +00:00
Devang Patel
14a55d952c Move up dwarf writer initialization in common AsmPrinter class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73784 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 21:54:26 +00:00
Eli Friedman
2fb070bf5a Minor cleanup; fixes review comments for a previous patch. Sorry for
taking so long to get to this!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73757 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 06:01:55 +00:00
Lang Hames
10382fb71d More VNInfo tweaking, plus a little progress on intra-block splitting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73750 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 02:17:53 +00:00
Chris Lattner
a93ca92379 move mangler quote handling from asm printers to TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73738 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:41:35 +00:00
Chris Lattner
b839c3f577 simplify macro debug info directive handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73736 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:31:37 +00:00
Lang Hames
d21c31610c Improved PHI def marking, replaced some gotos with breaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73727 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 22:01:47 +00:00
Evan Cheng
b13bafe5c1 On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73720 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 20:37:15 +00:00
Evan Cheng
f9f1da17f8 - Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 02:04:01 +00:00
Lang Hames
857c4e01f8 VNInfo cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73634 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 21:01:20 +00:00
Sanjiv Gupta
7d8d36a69f Fixed names of libcalls checked in r73480.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73483 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 10:22:58 +00:00
Sanjiv Gupta
8aa207ee30 Added required libcalls for PIC16 (mostly floating points to integer casting operations).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73480 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 09:03:58 +00:00
Evan Cheng
7b11365787 Rename RemoveCopiesFromValNo to TurnCopiesFromValNoToImpDefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73479 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 07:15:05 +00:00
Evan Cheng
67fcf56ac4 If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead.
TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 07:12:58 +00:00
Eli Friedman
db3c169f3a Add some generic expansion logic for SMULO and UMULO. Fixes UMULO
support for x86, and UMULO/SMULO for many architectures, including PPC 
(PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's
not bad.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73477 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 06:58:29 +00:00
Bill Wendling
05b5e03ec8 Fix typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73464 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 04:02:03 +00:00
Devang Patel
c2230821a6 Use MainCU if it is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73457 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 02:09:30 +00:00
Owen Anderson
be24f1b7fb Owen Anderson 2009-06-15: Use a SmallPtrSet here, for speed and to match df_iterator.
Owen Anderson 2009-06-15: Remember to clear out our maps to prevent crashing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73438 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 22:54:48 +00:00
Dan Gohman
15480bd174 Change this from an assert to a cerr+exit, since it's diagnosing an
unsupported inline asm construct, rather than verifying a code invariant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73435 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 22:32:41 +00:00
Devang Patel
11a407f43f Gracefully handle imbalanced inline function begin and end markers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73426 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 21:45:50 +00:00
Evan Cheng
2077e18caf ifcvt should ignore cfg where true and false successors are the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 21:24:34 +00:00
Arnold Schwaighofer
5d2c01e48a CheckTailCallReturnConstraints is missing a check on the
incomming chain of the RETURN node. The incomming chain must
be the outgoing chain of the CALL node. This causes the
backend to identify tail calls that are not tail calls. This
patch fixes this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73387 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 14:43:36 +00:00
Evan Cheng
358dec5180 Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 08:28:29 +00:00
Dan Gohman
a119de86a0 Fix old-style type names in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73362 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14 23:30:43 +00:00
Evan Cheng
90f95f88c6 Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14 20:22:55 +00:00
Bruno Cardoso Lopes
ae9163f0e2 Introduce new BinaryObject (blob) class, ELF Writer modified to use it. BinaryObject.h by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73333 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14 07:53:21 +00:00
Evan Cheng
e7d6df7353 Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-13 09:12:55 +00:00
Devang Patel
daf9e02893 llvm.dbg.region.end() intrinsic is not required to be in _last_ basic block in a function. If that happens then any basic block that follows (lexically) the block with regin.end will not have scope info available. LexicalScopeStack relies on processing basic block in CFG order, but this processing order is not guaranteed. Things get complicated when the optimizer gets a chance to optimizer IR with dbg intrinsics.
Apply defensive patch to preserve at least one lexical scope till the end of function.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73282 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-13 02:16:18 +00:00
Owen Anderson
a21f31bca5 Improve style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73258 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 22:07:19 +00:00
Owen Anderson
5b6139a4d1 This is supposed to be a preorder numbering of the dominator tree, not the CFG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73257 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 21:50:22 +00:00
Owen Anderson
fdf72c6607 Now with less iterator invalidation, and other forms of crashing!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73256 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 21:41:29 +00:00
Evan Cheng
4a274e573d If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73255 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 21:34:26 +00:00
Devang Patel
9217f793bf Clear AbstractInstanceRootMap at the end of the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73244 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 19:24:05 +00:00
Bruno Cardoso Lopes
c997d45ae5 Support for ELF Visibility
Emission for globals, using the correct data sections
Function alignment can be computed for each target using TargetELFWriterInfo
Some small fixes



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73201 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-11 19:16:03 +00:00
Oscar Fuentes
89456cecb3 CMake: Updated list of files on lib/CodeGen/CMakeLists.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73174 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-10 22:53:59 +00:00
Sanjiv Gupta
cb597c9cc4 Remove warnings: no newline at end of file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73156 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-10 03:42:13 +00:00
Owen Anderson
6cbd8da86e Add the beginnings of an implementatation of lazy liveness analysis, based on "Fast Liveness Checking for SSA-form Programs" by Boissinot, et al.
This is still very early, hasn't been tested, and is not yet well documented.  More to come soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73141 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-09 19:30:45 +00:00
Bruno Cardoso Lopes
06bfa33eef Delete comment and fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73040 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07 21:49:11 +00:00
Bruno Cardoso Lopes
24f14f16fd Fix wrong elf class and byte order initializations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73039 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07 21:33:20 +00:00
Bruno Cardoso Lopes
a029a27fae Simple ELF32/64 binary files can now be emitted for x86 and x86_64 without
relocation sections.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73038 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07 21:22:38 +00:00
Eli Friedman
f10d3a7bcd Tweak the expansion code for BIT_CONVERT to generate better code
converting from an MMX vector to an i64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07 09:41:57 +00:00
Eli Friedman
7a5e55509b Slightly generalize the code that handles shuffles of consecutive loads
on x86 to handle more cases.  Fix a bug in said code that would cause it 
to read past the end of an object.  Rewrite the code in 
SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. 
Remove PerformBuildVectorCombine, which is no longer necessary with 
these changes.  In addition to simplifying the code, with this change, 
we can now catch a few more cases of consecutive loads.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73012 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07 06:52:44 +00:00
Eli Friedman
5257106c4d Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal
types.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72993 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 07:08:26 +00:00
Eli Friedman
7ef3d17866 Factor out a couple of helpers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72992 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 07:04:42 +00:00
Bruno Cardoso Lopes
f5b0c5a1c7 Remove elf specific info from ELFWriter.h to Elf.h. Code cleanup and more comments added
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72982 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 03:56:29 +00:00
Eli Friedman
556929a84b Make SINT_TO_FP/UINT_TO_FP vector legalization queries query on the
integer type to be consistent with normal operation legalization.  No visible
change because nothing is actually using this at the moment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72980 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 03:27:50 +00:00
Devang Patel
578efa920a Add new function attribute - noimplicitfloat
Update code generator to use this attribute and remove NoImplicitFloat target option.
Update llc to set this attribute when -no-implicit-float command line option is used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72959 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 21:57:13 +00:00
Nate Begeman
abc0199680 Adapt the x86 build_vector dagcombine to the current state of the legalizer.
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector 
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.

Teach the build_vector dag combine in x86 back end to recognize consecutive 
loads producing the low part of the vector.

Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.

Add a testcase for the transform.

Old:
	subl	$28, %esp
	movl	32(%esp), %eax
	movl	4(%eax), %ecx
	movl	%ecx, 4(%esp)
	movl	(%eax), %eax
	movl	%eax, (%esp)
	movaps	(%esp), %xmm0
	pmovzxwd	%xmm0, %xmm0
	movl	36(%esp), %eax
	movaps	%xmm0, (%eax)
	addl	$28, %esp
	ret

New:
	movl	4(%esp), %eax
	pmovzxwd	(%eax), %xmm0
	movl	8(%esp), %eax
	movaps	%xmm0, (%eax)
	ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72957 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 21:37:30 +00:00
Dan Gohman
c965ee223c Remove some unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72948 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 16:32:58 +00:00
Sanjiv Gupta
a43a7aefd7 Allow libcalls for i16 sdiv/udiv/rem operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72941 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 14:41:10 +00:00