llvm-6502/lib/CodeGen
2009-06-10 22:53:59 +00:00
..
AsmPrinter Remove some unnecessary #includes. 2009-06-05 16:32:58 +00:00
SelectionDAG Tweak the expansion code for BIT_CONVERT to generate better code 2009-06-07 09:41:57 +00:00
BranchFolding.cpp Fix PR4188. TailMerging can't tolerate inexact 2009-05-11 21:54:13 +00:00
CMakeLists.txt CMake: Updated list of files on lib/CodeGen/CMakeLists.txt. 2009-06-10 22:53:59 +00:00
CodePlacementOpt.cpp Fix CodePlacementOpt::OptimizeIntraLoopEdges so that its return value 2009-05-18 21:02:18 +00:00
DeadMachineInstructionElim.cpp
DwarfEHPrepare.cpp Add a new codegen pass that normalizes dwarf exception handling 2009-05-22 20:36:31 +00:00
ELF.h Delete comment and fix typo 2009-06-07 21:49:11 +00:00
ELFCodeEmitter.cpp Simple ELF32/64 binary files can now be emitted for x86 and x86_64 without 2009-06-07 21:22:38 +00:00
ELFCodeEmitter.h Simple ELF32/64 binary files can now be emitted for x86 and x86_64 without 2009-06-07 21:22:38 +00:00
ELFWriter.cpp Delete comment and fix typo 2009-06-07 21:49:11 +00:00
ELFWriter.h Simple ELF32/64 binary files can now be emitted for x86 and x86_64 without 2009-06-07 21:22:38 +00:00
GCMetadata.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
IfConversion.cpp Revert r71744. I must not have understood this correctly, because the 2009-05-14 18:08:41 +00:00
IntrinsicLowering.cpp Switch to using IRBuilder throughout. 2009-05-12 20:27:44 +00:00
LatencyPriorityQueue.cpp
LazyLiveness.cpp Remove warnings: no newline at end of file. 2009-06-10 03:42:13 +00:00
LiveInterval.cpp Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. 2009-06-02 16:53:25 +00:00
LiveIntervalAnalysis.cpp Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. 2009-06-02 16:53:25 +00:00
LiveStackAnalysis.cpp Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. 2009-06-02 16:53:25 +00:00
LiveVariables.cpp If there is a def of a super-register followed by a use of a sub-register, do *not* add an implicit def of the sub-register. e.g. 2009-06-03 05:15:46 +00:00
LLVMTargetMachine.cpp First patch in the direction of splitting MachineCodeEmitter in two subclasses: 2009-05-30 20:51:52 +00:00
LowerSubregs.cpp Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86 2009-03-23 07:19:58 +00:00
MachineBasicBlock.cpp If a MachineBasicBlock has multiple ways of reaching another block, 2009-05-05 21:10:19 +00:00
MachineDominators.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
MachineFunction.cpp Temporarily revert r72191. It was causing an assert during llvm-gcc 2009-05-21 00:04:55 +00:00
MachineInstr.cpp Remove some unnecessary #includes. 2009-06-05 16:32:58 +00:00
MachineLICM.cpp MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. 2009-02-27 00:02:22 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp DebugLabelFolder ruthlessly deletes redundant labels. However, sometimes the redundant labels is referenced by debug info somewhere else. This patch provies a way so that dwarf writer can mark labels as used. 2009-04-10 18:58:59 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Move MachineRegisterInfo::setRegClass out of line. 2009-04-15 01:19:35 +00:00
MachineSink.cpp fix two problems with machine sinking: 2009-04-10 16:38:36 +00:00
MachineVerifier.cpp Rename MachineVerifier pass to avoid command line collision. 2009-05-17 19:37:14 +00:00
MachO.h Move structures and classes into header files, providing two new headers and 2009-06-03 03:43:31 +00:00
MachOCodeEmitter.cpp Move structures and classes into header files, providing two new headers and 2009-06-03 03:43:31 +00:00
MachOCodeEmitter.h Move structures and classes into header files, providing two new headers and 2009-06-03 03:43:31 +00:00
MachOWriter.cpp Move structures and classes into header files, providing two new headers and 2009-06-03 03:43:31 +00:00
MachOWriter.h Move structures and classes into header files, providing two new headers and 2009-06-03 03:43:31 +00:00
Makefile Removed trailing whitespace from Makefiles. 2009-01-09 16:44:42 +00:00
OcamlGC.cpp Registry.h should not depend on CommandLine.h. 2009-01-16 07:02:28 +00:00
Passes.cpp
PBQP.cpp
PBQP.h
PHIElimination.cpp LiveVariables::VarInfo contains an AliveBlocks BitVector, which has as many 2009-05-26 18:27:15 +00:00
PostRASchedulerList.cpp Move getInstrOperandRegClass from the scheduler to TargetInstrInfo. 2009-05-05 00:30:09 +00:00
PreAllocSplitting.cpp In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. 2009-05-03 18:32:42 +00:00
PrologEpilogInserter.cpp Removing the HasBuiltinSetjmp flag and associated bits. Flagging the presence 2009-05-13 23:50:53 +00:00
PrologEpilogInserter.h PEI: rename PEI.h to PrologEpilogInserter.h to adhere to file naming standard 2009-05-13 17:52:11 +00:00
PseudoSourceValue.cpp Now that errs() is properly non-buffered, there's no need to 2009-03-23 15:57:19 +00:00
README.txt
RegAllocBigBlock.cpp Adjust the sizes for a few SmallVectors to reflect their usage. 2009-02-12 17:29:01 +00:00
RegAllocLinearScan.cpp RALinScan::attemptTrivialCoalescing() was returning a virtual register instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets. 2009-06-04 20:53:36 +00:00
RegAllocLocal.cpp Fix pr4100. Do not remove no-op copies when they are dead. The register 2009-05-07 23:47:03 +00:00
RegAllocPBQP.cpp Untabification. 2009-05-30 01:09:53 +00:00
RegAllocSimple.cpp Fix pr3954. The register scavenger asserts for inline assembly with 2009-04-09 17:16:43 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp Fix pr3954. The register scavenger asserts for inline assembly with 2009-04-09 17:16:43 +00:00
ScheduleDAG.cpp When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGEmit.cpp When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGInstrs.cpp When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGInstrs.h When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGPrinter.cpp Apparently some MachineBasicBlock's don't have corresponding llvm basic blocks. 2009-02-11 23:42:39 +00:00
ShadowStackGC.cpp Introduce new linkage types linkonce_odr, weak_odr, common_odr 2009-03-07 15:45:40 +00:00
ShrinkWrapping.cpp PEI: rename PEI.h to PrologEpilogInserter.h to adhere to file naming standard 2009-05-13 17:52:11 +00:00
SimpleRegisterCoalescing.cpp Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. 2009-06-02 16:53:25 +00:00
SimpleRegisterCoalescing.h Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. 2009-06-02 16:53:25 +00:00
Spiller.cpp Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. 2009-06-02 16:53:25 +00:00
Spiller.h Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. 2009-06-02 16:53:25 +00:00
StackProtector.cpp Rename PaddedSize to AllocSize, in the hope that this 2009-05-09 07:06:46 +00:00
StackSlotColoring.cpp Fixed a stack slot coloring with reg bug: do not update implicit use / def when doing forward / backward propagation. 2009-05-12 18:31:57 +00:00
StrongPHIElimination.cpp Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. 2009-06-02 16:53:25 +00:00
TargetInstrInfoImpl.cpp Change MachineInstrBuilder::addReg() to take a flag instead of a list of 2009-05-13 21:33:08 +00:00
TwoAddressInstructionPass.cpp Eliminate VarInfo::UsedBlocks. 2009-05-26 06:25:46 +00:00
UnreachableBlockElim.cpp Rename getAnalysisToUpdate to getAnalysisIfAvailable. 2009-01-28 13:14:17 +00:00
VirtRegMap.cpp Restore minor deletion. 2009-05-04 18:40:41 +00:00
VirtRegMap.h Restore minor deletion. 2009-05-04 18:40:41 +00:00
VirtRegRewriter.cpp Removed SimpleRewriter. 2009-06-04 18:45:36 +00:00
VirtRegRewriter.h Renamed Spiller classes (plus uses and related files) to VirtRegRewriter. 2009-05-06 02:36:21 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4